18c2ecf20Sopenharmony_ciSpreadtrum SC9860 Clock Binding 28c2ecf20Sopenharmony_ci------------------------ 38c2ecf20Sopenharmony_ci 48c2ecf20Sopenharmony_ciRequired properties: 58c2ecf20Sopenharmony_ci- compatible: should contain the following compatible strings: 68c2ecf20Sopenharmony_ci - "sprd,sc9860-pmu-gate" 78c2ecf20Sopenharmony_ci - "sprd,sc9860-pll" 88c2ecf20Sopenharmony_ci - "sprd,sc9860-ap-clk" 98c2ecf20Sopenharmony_ci - "sprd,sc9860-aon-prediv" 108c2ecf20Sopenharmony_ci - "sprd,sc9860-apahb-gate" 118c2ecf20Sopenharmony_ci - "sprd,sc9860-aon-gate" 128c2ecf20Sopenharmony_ci - "sprd,sc9860-aonsecure-clk" 138c2ecf20Sopenharmony_ci - "sprd,sc9860-agcp-gate" 148c2ecf20Sopenharmony_ci - "sprd,sc9860-gpu-clk" 158c2ecf20Sopenharmony_ci - "sprd,sc9860-vsp-clk" 168c2ecf20Sopenharmony_ci - "sprd,sc9860-vsp-gate" 178c2ecf20Sopenharmony_ci - "sprd,sc9860-cam-clk" 188c2ecf20Sopenharmony_ci - "sprd,sc9860-cam-gate" 198c2ecf20Sopenharmony_ci - "sprd,sc9860-disp-clk" 208c2ecf20Sopenharmony_ci - "sprd,sc9860-disp-gate" 218c2ecf20Sopenharmony_ci - "sprd,sc9860-apapb-gate" 228c2ecf20Sopenharmony_ci 238c2ecf20Sopenharmony_ci- #clock-cells: must be 1 248c2ecf20Sopenharmony_ci 258c2ecf20Sopenharmony_ci- clocks : Should be the input parent clock(s) phandle for the clock, this 268c2ecf20Sopenharmony_ci property here just simply shows which clock group the clocks' 278c2ecf20Sopenharmony_ci parents are in, since each clk node would represent many clocks 288c2ecf20Sopenharmony_ci which are defined in the driver. The detailed dependency 298c2ecf20Sopenharmony_ci relationship (i.e. how many parents and which are the parents) 308c2ecf20Sopenharmony_ci are implemented in driver code. 318c2ecf20Sopenharmony_ci 328c2ecf20Sopenharmony_ciOptional properties: 338c2ecf20Sopenharmony_ci 348c2ecf20Sopenharmony_ci- reg: Contain the registers base address and length. It must be configured 358c2ecf20Sopenharmony_ci only if no 'sprd,syscon' under the node. 368c2ecf20Sopenharmony_ci 378c2ecf20Sopenharmony_ci- sprd,syscon: phandle to the syscon which is in the same address area with 388c2ecf20Sopenharmony_ci the clock, and so we can get regmap for the clocks from the 398c2ecf20Sopenharmony_ci syscon device. 408c2ecf20Sopenharmony_ci 418c2ecf20Sopenharmony_ciExample: 428c2ecf20Sopenharmony_ci 438c2ecf20Sopenharmony_ci pmu_gate: pmu-gate { 448c2ecf20Sopenharmony_ci compatible = "sprd,sc9860-pmu-gate"; 458c2ecf20Sopenharmony_ci sprd,syscon = <&pmu_regs>; 468c2ecf20Sopenharmony_ci clocks = <&ext_26m>; 478c2ecf20Sopenharmony_ci #clock-cells = <1>; 488c2ecf20Sopenharmony_ci }; 498c2ecf20Sopenharmony_ci 508c2ecf20Sopenharmony_ci pll: pll { 518c2ecf20Sopenharmony_ci compatible = "sprd,sc9860-pll"; 528c2ecf20Sopenharmony_ci sprd,syscon = <&ana_regs>; 538c2ecf20Sopenharmony_ci clocks = <&pmu_gate 0>; 548c2ecf20Sopenharmony_ci #clock-cells = <1>; 558c2ecf20Sopenharmony_ci }; 568c2ecf20Sopenharmony_ci 578c2ecf20Sopenharmony_ci ap_clk: clock-controller@20000000 { 588c2ecf20Sopenharmony_ci compatible = "sprd,sc9860-ap-clk"; 598c2ecf20Sopenharmony_ci reg = <0 0x20000000 0 0x400>; 608c2ecf20Sopenharmony_ci clocks = <&ext_26m>, <&pll 0>, 618c2ecf20Sopenharmony_ci <&pmu_gate 0>; 628c2ecf20Sopenharmony_ci #clock-cells = <1>; 638c2ecf20Sopenharmony_ci }; 64