18c2ecf20Sopenharmony_ciBinding for the AXS10X Generic PLL clock 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciThis binding uses the common clock binding[1]. 48c2ecf20Sopenharmony_ci 58c2ecf20Sopenharmony_ci[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 68c2ecf20Sopenharmony_ci 78c2ecf20Sopenharmony_ciRequired properties: 88c2ecf20Sopenharmony_ci- compatible: should be "snps,axs10x-<name>-pll-clock" 98c2ecf20Sopenharmony_ci "snps,axs10x-arc-pll-clock" 108c2ecf20Sopenharmony_ci "snps,axs10x-pgu-pll-clock" 118c2ecf20Sopenharmony_ci- reg: should always contain 2 pairs address - length: first for PLL config 128c2ecf20Sopenharmony_ciregisters and second for corresponding LOCK CGU register. 138c2ecf20Sopenharmony_ci- clocks: shall be the input parent clock phandle for the PLL. 148c2ecf20Sopenharmony_ci- #clock-cells: from common clock binding; Should always be set to 0. 158c2ecf20Sopenharmony_ci 168c2ecf20Sopenharmony_ciExample: 178c2ecf20Sopenharmony_ci input-clk: input-clk { 188c2ecf20Sopenharmony_ci clock-frequency = <33333333>; 198c2ecf20Sopenharmony_ci compatible = "fixed-clock"; 208c2ecf20Sopenharmony_ci #clock-cells = <0>; 218c2ecf20Sopenharmony_ci }; 228c2ecf20Sopenharmony_ci 238c2ecf20Sopenharmony_ci core-clk: core-clk@80 { 248c2ecf20Sopenharmony_ci compatible = "snps,axs10x-arc-pll-clock"; 258c2ecf20Sopenharmony_ci reg = <0x80 0x10>, <0x100 0x10>; 268c2ecf20Sopenharmony_ci #clock-cells = <0>; 278c2ecf20Sopenharmony_ci clocks = <&input-clk>; 288c2ecf20Sopenharmony_ci }; 29