18c2ecf20Sopenharmony_ciBinding for the HSDK Generic PLL clock
28c2ecf20Sopenharmony_ci
38c2ecf20Sopenharmony_ciThis binding uses the common clock binding[1].
48c2ecf20Sopenharmony_ci
58c2ecf20Sopenharmony_ci[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
68c2ecf20Sopenharmony_ci
78c2ecf20Sopenharmony_ciRequired properties:
88c2ecf20Sopenharmony_ci- compatible: should be "snps,hsdk-<name>-pll-clock"
98c2ecf20Sopenharmony_ci  "snps,hsdk-core-pll-clock"
108c2ecf20Sopenharmony_ci  "snps,hsdk-gp-pll-clock"
118c2ecf20Sopenharmony_ci  "snps,hsdk-hdmi-pll-clock"
128c2ecf20Sopenharmony_ci- reg : should contain base register location and length.
138c2ecf20Sopenharmony_ci- clocks: shall be the input parent clock phandle for the PLL.
148c2ecf20Sopenharmony_ci- #clock-cells: from common clock binding; Should always be set to 0.
158c2ecf20Sopenharmony_ci
168c2ecf20Sopenharmony_ciExample:
178c2ecf20Sopenharmony_ci	input_clk: input-clk {
188c2ecf20Sopenharmony_ci		clock-frequency = <33333333>;
198c2ecf20Sopenharmony_ci		compatible = "fixed-clock";
208c2ecf20Sopenharmony_ci		#clock-cells = <0>;
218c2ecf20Sopenharmony_ci	};
228c2ecf20Sopenharmony_ci
238c2ecf20Sopenharmony_ci	cpu_clk: cpu-clk@0 {
248c2ecf20Sopenharmony_ci		compatible = "snps,hsdk-core-pll-clock";
258c2ecf20Sopenharmony_ci		reg = <0x00 0x10>;
268c2ecf20Sopenharmony_ci		#clock-cells = <0>;
278c2ecf20Sopenharmony_ci		clocks = <&input_clk>;
288c2ecf20Sopenharmony_ci	};
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