18c2ecf20Sopenharmony_ci* Samsung S3C64xx Clock Controller
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38c2ecf20Sopenharmony_ciThe S3C64xx clock controller generates and supplies clock to various controllers
48c2ecf20Sopenharmony_ciwithin the SoC. The clock binding described here is applicable to all SoCs in
58c2ecf20Sopenharmony_cithe S3C64xx family.
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78c2ecf20Sopenharmony_ciRequired Properties:
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98c2ecf20Sopenharmony_ci- compatible: should be one of the following.
108c2ecf20Sopenharmony_ci  - "samsung,s3c6400-clock" - controller compatible with S3C6400 SoC.
118c2ecf20Sopenharmony_ci  - "samsung,s3c6410-clock" - controller compatible with S3C6410 SoC.
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138c2ecf20Sopenharmony_ci- reg: physical base address of the controller and length of memory mapped
148c2ecf20Sopenharmony_ci  region.
158c2ecf20Sopenharmony_ci
168c2ecf20Sopenharmony_ci- #clock-cells: should be 1.
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188c2ecf20Sopenharmony_ciEach clock is assigned an identifier and client nodes can use this identifier
198c2ecf20Sopenharmony_cito specify the clock which they consume. Some of the clocks are available only
208c2ecf20Sopenharmony_cion a particular S3C64xx SoC and this is specified where applicable.
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228c2ecf20Sopenharmony_ciAll available clocks are defined as preprocessor macros in
238c2ecf20Sopenharmony_cidt-bindings/clock/samsung,s3c64xx-clock.h header and can be used in device
248c2ecf20Sopenharmony_citree sources.
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268c2ecf20Sopenharmony_ciExternal clocks:
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288c2ecf20Sopenharmony_ciThere are several clocks that are generated outside the SoC. It is expected
298c2ecf20Sopenharmony_cithat they are defined using standard clock bindings with following
308c2ecf20Sopenharmony_ciclock-output-names:
318c2ecf20Sopenharmony_ci - "fin_pll" - PLL input clock (xtal/extclk) - required,
328c2ecf20Sopenharmony_ci - "xusbxti" - USB xtal - required,
338c2ecf20Sopenharmony_ci - "iiscdclk0" - I2S0 codec clock - optional,
348c2ecf20Sopenharmony_ci - "iiscdclk1" - I2S1 codec clock - optional,
358c2ecf20Sopenharmony_ci - "iiscdclk2" - I2S2 codec clock - optional,
368c2ecf20Sopenharmony_ci - "pcmcdclk0" - PCM0 codec clock - optional,
378c2ecf20Sopenharmony_ci - "pcmcdclk1" - PCM1 codec clock - optional, only S3C6410.
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398c2ecf20Sopenharmony_ciExample: Clock controller node:
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418c2ecf20Sopenharmony_ci	clock: clock-controller@7e00f000 {
428c2ecf20Sopenharmony_ci		compatible = "samsung,s3c6410-clock";
438c2ecf20Sopenharmony_ci		reg = <0x7e00f000 0x1000>;
448c2ecf20Sopenharmony_ci		#clock-cells = <1>;
458c2ecf20Sopenharmony_ci	};
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478c2ecf20Sopenharmony_ciExample: Required external clocks:
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498c2ecf20Sopenharmony_ci	fin_pll: clock-fin-pll {
508c2ecf20Sopenharmony_ci		compatible = "fixed-clock";
518c2ecf20Sopenharmony_ci		clock-output-names = "fin_pll";
528c2ecf20Sopenharmony_ci		clock-frequency = <12000000>;
538c2ecf20Sopenharmony_ci		#clock-cells = <0>;
548c2ecf20Sopenharmony_ci	};
558c2ecf20Sopenharmony_ci
568c2ecf20Sopenharmony_ci	xusbxti: clock-xusbxti {
578c2ecf20Sopenharmony_ci		compatible = "fixed-clock";
588c2ecf20Sopenharmony_ci		clock-output-names = "xusbxti";
598c2ecf20Sopenharmony_ci		clock-frequency = <48000000>;
608c2ecf20Sopenharmony_ci		#clock-cells = <0>;
618c2ecf20Sopenharmony_ci	};
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638c2ecf20Sopenharmony_ciExample: UART controller node that consumes the clock generated by the clock
648c2ecf20Sopenharmony_ci  controller (refer to the standard clock bindings for information about
658c2ecf20Sopenharmony_ci  "clocks" and "clock-names" properties):
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678c2ecf20Sopenharmony_ci		uart0: serial@7f005000 {
688c2ecf20Sopenharmony_ci			compatible = "samsung,s3c6400-uart";
698c2ecf20Sopenharmony_ci			reg = <0x7f005000 0x100>;
708c2ecf20Sopenharmony_ci			interrupt-parent = <&vic1>;
718c2ecf20Sopenharmony_ci			interrupts = <5>;
728c2ecf20Sopenharmony_ci			clock-names = "uart", "clk_uart_baud2",
738c2ecf20Sopenharmony_ci					"clk_uart_baud3";
748c2ecf20Sopenharmony_ci			clocks = <&clock PCLK_UART0>, <&clocks PCLK_UART0>,
758c2ecf20Sopenharmony_ci					<&clock SCLK_UART>;
768c2ecf20Sopenharmony_ci		};
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