18c2ecf20Sopenharmony_ci* Rockchip RK3308 Clock and Reset Unit 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciThe RK3308 clock controller generates and supplies clock to various 48c2ecf20Sopenharmony_cicontrollers within the SoC and also implements a reset controller for SoC 58c2ecf20Sopenharmony_ciperipherals. 68c2ecf20Sopenharmony_ci 78c2ecf20Sopenharmony_ciRequired Properties: 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_ci- compatible: CRU should be "rockchip,rk3308-cru" 108c2ecf20Sopenharmony_ci- reg: physical base address of the controller and length of memory mapped 118c2ecf20Sopenharmony_ci region. 128c2ecf20Sopenharmony_ci- #clock-cells: should be 1. 138c2ecf20Sopenharmony_ci- #reset-cells: should be 1. 148c2ecf20Sopenharmony_ci 158c2ecf20Sopenharmony_ciOptional Properties: 168c2ecf20Sopenharmony_ci 178c2ecf20Sopenharmony_ci- rockchip,grf: phandle to the syscon managing the "general register files" 188c2ecf20Sopenharmony_ci If missing, pll rates are not changeable, due to the missing pll lock status. 198c2ecf20Sopenharmony_ci 208c2ecf20Sopenharmony_ciEach clock is assigned an identifier and client nodes can use this identifier 218c2ecf20Sopenharmony_cito specify the clock which they consume. All available clocks are defined as 228c2ecf20Sopenharmony_cipreprocessor macros in the dt-bindings/clock/rk3308-cru.h headers and can be 238c2ecf20Sopenharmony_ciused in device tree sources. Similar macros exist for the reset sources in 248c2ecf20Sopenharmony_cithese files. 258c2ecf20Sopenharmony_ci 268c2ecf20Sopenharmony_ciExternal clocks: 278c2ecf20Sopenharmony_ci 288c2ecf20Sopenharmony_ciThere are several clocks that are generated outside the SoC. It is expected 298c2ecf20Sopenharmony_cithat they are defined using standard clock bindings with following 308c2ecf20Sopenharmony_ciclock-output-names: 318c2ecf20Sopenharmony_ci - "xin24m" - crystal input - required, 328c2ecf20Sopenharmony_ci - "xin32k" - rtc clock - optional, 338c2ecf20Sopenharmony_ci - "mclk_i2s0_8ch_in", "mclk_i2s1_8ch_in", "mclk_i2s2_8ch_in", 348c2ecf20Sopenharmony_ci "mclk_i2s3_8ch_in", "mclk_i2s0_2ch_in", 358c2ecf20Sopenharmony_ci "mclk_i2s1_2ch_in" - external I2S or SPDIF clock - optional, 368c2ecf20Sopenharmony_ci - "mac_clkin" - external MAC clock - optional 378c2ecf20Sopenharmony_ci 388c2ecf20Sopenharmony_ciExample: Clock controller node: 398c2ecf20Sopenharmony_ci 408c2ecf20Sopenharmony_ci cru: clock-controller@ff500000 { 418c2ecf20Sopenharmony_ci compatible = "rockchip,rk3308-cru"; 428c2ecf20Sopenharmony_ci reg = <0x0 0xff500000 0x0 0x1000>; 438c2ecf20Sopenharmony_ci rockchip,grf = <&grf>; 448c2ecf20Sopenharmony_ci #clock-cells = <1>; 458c2ecf20Sopenharmony_ci #reset-cells = <1>; 468c2ecf20Sopenharmony_ci }; 478c2ecf20Sopenharmony_ci 488c2ecf20Sopenharmony_ciExample: UART controller node that consumes the clock generated by the clock 498c2ecf20Sopenharmony_ci controller: 508c2ecf20Sopenharmony_ci 518c2ecf20Sopenharmony_ci uart0: serial@ff0a0000 { 528c2ecf20Sopenharmony_ci compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 538c2ecf20Sopenharmony_ci reg = <0x0 0xff0a0000 0x0 0x100>; 548c2ecf20Sopenharmony_ci interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 558c2ecf20Sopenharmony_ci clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 568c2ecf20Sopenharmony_ci clock-names = "baudclk", "apb_pclk"; 578c2ecf20Sopenharmony_ci reg-shift = <2>; 588c2ecf20Sopenharmony_ci reg-io-width = <4>; 598c2ecf20Sopenharmony_ci status = "disabled"; 608c2ecf20Sopenharmony_ci }; 61