18c2ecf20Sopenharmony_ci* Renesas H8/300 divider clock
28c2ecf20Sopenharmony_ci
38c2ecf20Sopenharmony_ciRequired Properties:
48c2ecf20Sopenharmony_ci
58c2ecf20Sopenharmony_ci  - compatible: Must be "renesas,h8300-div-clock"
68c2ecf20Sopenharmony_ci
78c2ecf20Sopenharmony_ci  - clocks: Reference to the parent clocks ("extal1" and "extal2")
88c2ecf20Sopenharmony_ci
98c2ecf20Sopenharmony_ci  - #clock-cells: Must be 1
108c2ecf20Sopenharmony_ci
118c2ecf20Sopenharmony_ci  - reg: Base address and length of the divide rate selector
128c2ecf20Sopenharmony_ci
138c2ecf20Sopenharmony_ci  - renesas,width: bit width of selector
148c2ecf20Sopenharmony_ci
158c2ecf20Sopenharmony_ciExample
168c2ecf20Sopenharmony_ci-------
178c2ecf20Sopenharmony_ci
188c2ecf20Sopenharmony_ci		cclk: cclk {
198c2ecf20Sopenharmony_ci			compatible = "renesas,h8300-div-clock";
208c2ecf20Sopenharmony_ci			clocks = <&xclk>;
218c2ecf20Sopenharmony_ci			#clock-cells = <0>;
228c2ecf20Sopenharmony_ci			reg = <0xfee01b 2>;
238c2ecf20Sopenharmony_ci			renesas,width = <2>;
248c2ecf20Sopenharmony_ci		};
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