18c2ecf20Sopenharmony_ciQualcomm LPASS Clock Controller Binding 28c2ecf20Sopenharmony_ci----------------------------------------------- 38c2ecf20Sopenharmony_ci 48c2ecf20Sopenharmony_ciRequired properties : 58c2ecf20Sopenharmony_ci- compatible : shall contain "qcom,sdm845-lpasscc" 68c2ecf20Sopenharmony_ci- #clock-cells : from common clock binding, shall contain 1. 78c2ecf20Sopenharmony_ci- reg : shall contain base register address and size, 88c2ecf20Sopenharmony_ci in the order 98c2ecf20Sopenharmony_ci Index-0 maps to LPASS_CC register region 108c2ecf20Sopenharmony_ci Index-1 maps to LPASS_QDSP6SS register region 118c2ecf20Sopenharmony_ci 128c2ecf20Sopenharmony_ciOptional properties : 138c2ecf20Sopenharmony_ci- reg-names : register names of LPASS domain 148c2ecf20Sopenharmony_ci "cc", "qdsp6ss". 158c2ecf20Sopenharmony_ci 168c2ecf20Sopenharmony_ciExample: 178c2ecf20Sopenharmony_ci 188c2ecf20Sopenharmony_ciThe below node has to be defined in the cases where the LPASS peripheral loader 198c2ecf20Sopenharmony_ciwould bring the subsystem out of reset. 208c2ecf20Sopenharmony_ci 218c2ecf20Sopenharmony_ci lpasscc: clock-controller@17014000 { 228c2ecf20Sopenharmony_ci compatible = "qcom,sdm845-lpasscc"; 238c2ecf20Sopenharmony_ci reg = <0x17014000 0x1f004>, <0x17300000 0x200>; 248c2ecf20Sopenharmony_ci reg-names = "cc", "qdsp6ss"; 258c2ecf20Sopenharmony_ci #clock-cells = <1>; 268c2ecf20Sopenharmony_ci }; 27