18c2ecf20Sopenharmony_ci# SPDX-License-Identifier: GPL-2.0-only
28c2ecf20Sopenharmony_ci%YAML 1.2
38c2ecf20Sopenharmony_ci---
48c2ecf20Sopenharmony_ci$id: http://devicetree.org/schemas/clock/qcom,gpucc.yaml#
58c2ecf20Sopenharmony_ci$schema: http://devicetree.org/meta-schemas/core.yaml#
68c2ecf20Sopenharmony_ci
78c2ecf20Sopenharmony_cititle: Qualcomm Graphics Clock & Reset Controller Binding
88c2ecf20Sopenharmony_ci
98c2ecf20Sopenharmony_cimaintainers:
108c2ecf20Sopenharmony_ci  - Taniya Das <tdas@codeaurora.org>
118c2ecf20Sopenharmony_ci
128c2ecf20Sopenharmony_cidescription: |
138c2ecf20Sopenharmony_ci  Qualcomm graphics clock control module which supports the clocks, resets and
148c2ecf20Sopenharmony_ci  power domains on SDM845/SC7180/SM8150/SM8250.
158c2ecf20Sopenharmony_ci
168c2ecf20Sopenharmony_ci  See also:
178c2ecf20Sopenharmony_ci    dt-bindings/clock/qcom,gpucc-sdm845.h
188c2ecf20Sopenharmony_ci    dt-bindings/clock/qcom,gpucc-sc7180.h
198c2ecf20Sopenharmony_ci    dt-bindings/clock/qcom,gpucc-sm8150.h
208c2ecf20Sopenharmony_ci    dt-bindings/clock/qcom,gpucc-sm8250.h
218c2ecf20Sopenharmony_ci
228c2ecf20Sopenharmony_ciproperties:
238c2ecf20Sopenharmony_ci  compatible:
248c2ecf20Sopenharmony_ci    enum:
258c2ecf20Sopenharmony_ci      - qcom,sdm845-gpucc
268c2ecf20Sopenharmony_ci      - qcom,sc7180-gpucc
278c2ecf20Sopenharmony_ci      - qcom,sm8150-gpucc
288c2ecf20Sopenharmony_ci      - qcom,sm8250-gpucc
298c2ecf20Sopenharmony_ci
308c2ecf20Sopenharmony_ci  clocks:
318c2ecf20Sopenharmony_ci    items:
328c2ecf20Sopenharmony_ci      - description: Board XO source
338c2ecf20Sopenharmony_ci      - description: GPLL0 main branch source
348c2ecf20Sopenharmony_ci      - description: GPLL0 div branch source
358c2ecf20Sopenharmony_ci
368c2ecf20Sopenharmony_ci  clock-names:
378c2ecf20Sopenharmony_ci    items:
388c2ecf20Sopenharmony_ci      - const: bi_tcxo
398c2ecf20Sopenharmony_ci      - const: gcc_gpu_gpll0_clk_src
408c2ecf20Sopenharmony_ci      - const: gcc_gpu_gpll0_div_clk_src
418c2ecf20Sopenharmony_ci
428c2ecf20Sopenharmony_ci  '#clock-cells':
438c2ecf20Sopenharmony_ci    const: 1
448c2ecf20Sopenharmony_ci
458c2ecf20Sopenharmony_ci  '#reset-cells':
468c2ecf20Sopenharmony_ci    const: 1
478c2ecf20Sopenharmony_ci
488c2ecf20Sopenharmony_ci  '#power-domain-cells':
498c2ecf20Sopenharmony_ci    const: 1
508c2ecf20Sopenharmony_ci
518c2ecf20Sopenharmony_ci  reg:
528c2ecf20Sopenharmony_ci    maxItems: 1
538c2ecf20Sopenharmony_ci
548c2ecf20Sopenharmony_cirequired:
558c2ecf20Sopenharmony_ci  - compatible
568c2ecf20Sopenharmony_ci  - reg
578c2ecf20Sopenharmony_ci  - clocks
588c2ecf20Sopenharmony_ci  - clock-names
598c2ecf20Sopenharmony_ci  - '#clock-cells'
608c2ecf20Sopenharmony_ci  - '#reset-cells'
618c2ecf20Sopenharmony_ci  - '#power-domain-cells'
628c2ecf20Sopenharmony_ci
638c2ecf20Sopenharmony_ciadditionalProperties: false
648c2ecf20Sopenharmony_ci
658c2ecf20Sopenharmony_ciexamples:
668c2ecf20Sopenharmony_ci  - |
678c2ecf20Sopenharmony_ci    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
688c2ecf20Sopenharmony_ci    #include <dt-bindings/clock/qcom,rpmh.h>
698c2ecf20Sopenharmony_ci    clock-controller@5090000 {
708c2ecf20Sopenharmony_ci      compatible = "qcom,sdm845-gpucc";
718c2ecf20Sopenharmony_ci      reg = <0x05090000 0x9000>;
728c2ecf20Sopenharmony_ci      clocks = <&rpmhcc RPMH_CXO_CLK>,
738c2ecf20Sopenharmony_ci               <&gcc GCC_GPU_GPLL0_CLK_SRC>,
748c2ecf20Sopenharmony_ci               <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
758c2ecf20Sopenharmony_ci      clock-names = "bi_tcxo",
768c2ecf20Sopenharmony_ci                    "gcc_gpu_gpll0_clk_src",
778c2ecf20Sopenharmony_ci                    "gcc_gpu_gpll0_div_clk_src";
788c2ecf20Sopenharmony_ci      #clock-cells = <1>;
798c2ecf20Sopenharmony_ci      #reset-cells = <1>;
808c2ecf20Sopenharmony_ci      #power-domain-cells = <1>;
818c2ecf20Sopenharmony_ci    };
828c2ecf20Sopenharmony_ci...
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