18c2ecf20Sopenharmony_ci# SPDX-License-Identifier: GPL-2.0-only 28c2ecf20Sopenharmony_ci%YAML 1.2 38c2ecf20Sopenharmony_ci--- 48c2ecf20Sopenharmony_ci$id: http://devicetree.org/schemas/clock/qcom,msm8998-gpucc.yaml# 58c2ecf20Sopenharmony_ci$schema: http://devicetree.org/meta-schemas/core.yaml# 68c2ecf20Sopenharmony_ci 78c2ecf20Sopenharmony_cititle: Qualcomm Graphics Clock & Reset Controller Binding for MSM8998 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_cimaintainers: 108c2ecf20Sopenharmony_ci - Taniya Das <tdas@codeaurora.org> 118c2ecf20Sopenharmony_ci 128c2ecf20Sopenharmony_cidescription: | 138c2ecf20Sopenharmony_ci Qualcomm graphics clock control module which supports the clocks, resets and 148c2ecf20Sopenharmony_ci power domains on MSM8998. 158c2ecf20Sopenharmony_ci 168c2ecf20Sopenharmony_ci See also dt-bindings/clock/qcom,gpucc-msm8998.h. 178c2ecf20Sopenharmony_ci 188c2ecf20Sopenharmony_ciproperties: 198c2ecf20Sopenharmony_ci compatible: 208c2ecf20Sopenharmony_ci const: qcom,msm8998-gpucc 218c2ecf20Sopenharmony_ci 228c2ecf20Sopenharmony_ci clocks: 238c2ecf20Sopenharmony_ci items: 248c2ecf20Sopenharmony_ci - description: Board XO source 258c2ecf20Sopenharmony_ci - description: GPLL0 main branch source (gcc_gpu_gpll0_clk_src) 268c2ecf20Sopenharmony_ci 278c2ecf20Sopenharmony_ci clock-names: 288c2ecf20Sopenharmony_ci items: 298c2ecf20Sopenharmony_ci - const: xo 308c2ecf20Sopenharmony_ci - const: gpll0 318c2ecf20Sopenharmony_ci 328c2ecf20Sopenharmony_ci '#clock-cells': 338c2ecf20Sopenharmony_ci const: 1 348c2ecf20Sopenharmony_ci 358c2ecf20Sopenharmony_ci '#reset-cells': 368c2ecf20Sopenharmony_ci const: 1 378c2ecf20Sopenharmony_ci 388c2ecf20Sopenharmony_ci '#power-domain-cells': 398c2ecf20Sopenharmony_ci const: 1 408c2ecf20Sopenharmony_ci 418c2ecf20Sopenharmony_ci reg: 428c2ecf20Sopenharmony_ci maxItems: 1 438c2ecf20Sopenharmony_ci 448c2ecf20Sopenharmony_cirequired: 458c2ecf20Sopenharmony_ci - compatible 468c2ecf20Sopenharmony_ci - reg 478c2ecf20Sopenharmony_ci - clocks 488c2ecf20Sopenharmony_ci - clock-names 498c2ecf20Sopenharmony_ci - '#clock-cells' 508c2ecf20Sopenharmony_ci - '#reset-cells' 518c2ecf20Sopenharmony_ci - '#power-domain-cells' 528c2ecf20Sopenharmony_ci 538c2ecf20Sopenharmony_ciadditionalProperties: false 548c2ecf20Sopenharmony_ci 558c2ecf20Sopenharmony_ciexamples: 568c2ecf20Sopenharmony_ci - | 578c2ecf20Sopenharmony_ci #include <dt-bindings/clock/qcom,gcc-msm8998.h> 588c2ecf20Sopenharmony_ci #include <dt-bindings/clock/qcom,rpmcc.h> 598c2ecf20Sopenharmony_ci clock-controller@5065000 { 608c2ecf20Sopenharmony_ci compatible = "qcom,msm8998-gpucc"; 618c2ecf20Sopenharmony_ci #clock-cells = <1>; 628c2ecf20Sopenharmony_ci #reset-cells = <1>; 638c2ecf20Sopenharmony_ci #power-domain-cells = <1>; 648c2ecf20Sopenharmony_ci reg = <0x05065000 0x9000>; 658c2ecf20Sopenharmony_ci clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0_OUT_MAIN>; 668c2ecf20Sopenharmony_ci clock-names = "xo", "gpll0"; 678c2ecf20Sopenharmony_ci }; 688c2ecf20Sopenharmony_ci... 69