18c2ecf20Sopenharmony_ciNVIDIA Tegra210 Clock And Reset Controller 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciThis binding uses the common clock binding: 48c2ecf20Sopenharmony_ciDocumentation/devicetree/bindings/clock/clock-bindings.txt 58c2ecf20Sopenharmony_ci 68c2ecf20Sopenharmony_ciThe CAR (Clock And Reset) Controller on Tegra is the HW module responsible 78c2ecf20Sopenharmony_cifor muxing and gating Tegra's clocks, and setting their rates. 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_ciRequired properties : 108c2ecf20Sopenharmony_ci- compatible : Should be "nvidia,tegra210-car" 118c2ecf20Sopenharmony_ci- reg : Should contain CAR registers location and length 128c2ecf20Sopenharmony_ci- clocks : Should contain phandle and clock specifiers for two clocks: 138c2ecf20Sopenharmony_ci the 32 KHz "32k_in". 148c2ecf20Sopenharmony_ci- #clock-cells : Should be 1. 158c2ecf20Sopenharmony_ci In clock consumers, this cell represents the clock ID exposed by the 168c2ecf20Sopenharmony_ci CAR. The assignments may be found in header file 178c2ecf20Sopenharmony_ci <dt-bindings/clock/tegra210-car.h>. 188c2ecf20Sopenharmony_ci- #reset-cells : Should be 1. 198c2ecf20Sopenharmony_ci In clock consumers, this cell represents the bit number in the CAR's 208c2ecf20Sopenharmony_ci array of CLK_RST_CONTROLLER_RST_DEVICES_* registers. 218c2ecf20Sopenharmony_ci 228c2ecf20Sopenharmony_ciExample SoC include file: 238c2ecf20Sopenharmony_ci 248c2ecf20Sopenharmony_ci/ { 258c2ecf20Sopenharmony_ci tegra_car: clock { 268c2ecf20Sopenharmony_ci compatible = "nvidia,tegra210-car"; 278c2ecf20Sopenharmony_ci reg = <0x60006000 0x1000>; 288c2ecf20Sopenharmony_ci #clock-cells = <1>; 298c2ecf20Sopenharmony_ci #reset-cells = <1>; 308c2ecf20Sopenharmony_ci }; 318c2ecf20Sopenharmony_ci 328c2ecf20Sopenharmony_ci usb@c5004000 { 338c2ecf20Sopenharmony_ci clocks = <&tegra_car TEGRA210_CLK_USB2>; 348c2ecf20Sopenharmony_ci }; 358c2ecf20Sopenharmony_ci}; 368c2ecf20Sopenharmony_ci 378c2ecf20Sopenharmony_ciExample board file: 388c2ecf20Sopenharmony_ci 398c2ecf20Sopenharmony_ci/ { 408c2ecf20Sopenharmony_ci clocks { 418c2ecf20Sopenharmony_ci compatible = "simple-bus"; 428c2ecf20Sopenharmony_ci #address-cells = <1>; 438c2ecf20Sopenharmony_ci #size-cells = <0>; 448c2ecf20Sopenharmony_ci 458c2ecf20Sopenharmony_ci clk_32k: clock@1 { 468c2ecf20Sopenharmony_ci compatible = "fixed-clock"; 478c2ecf20Sopenharmony_ci reg = <1>; 488c2ecf20Sopenharmony_ci #clock-cells = <0>; 498c2ecf20Sopenharmony_ci clock-frequency = <32768>; 508c2ecf20Sopenharmony_ci }; 518c2ecf20Sopenharmony_ci }; 528c2ecf20Sopenharmony_ci 538c2ecf20Sopenharmony_ci &tegra_car { 548c2ecf20Sopenharmony_ci clocks = <&clk_32k>; 558c2ecf20Sopenharmony_ci }; 568c2ecf20Sopenharmony_ci}; 57