18c2ecf20Sopenharmony_ci* Nuvoton NPCM7XX Clock Controller
28c2ecf20Sopenharmony_ci
38c2ecf20Sopenharmony_ciNuvoton Poleg BMC NPCM7XX contains an integrated clock controller, which
48c2ecf20Sopenharmony_cigenerates and supplies clocks to all modules within the BMC.
58c2ecf20Sopenharmony_ci
68c2ecf20Sopenharmony_ciExternal clocks:
78c2ecf20Sopenharmony_ci
88c2ecf20Sopenharmony_ciThere are six fixed clocks that are generated outside the BMC. All clocks are of
98c2ecf20Sopenharmony_cia known fixed value that cannot be changed. clk_refclk, clk_mcbypck and
108c2ecf20Sopenharmony_ciclk_sysbypck are inputs to the clock controller.
118c2ecf20Sopenharmony_ciclk_rg1refck, clk_rg2refck and clk_xin are external clocks suppling the
128c2ecf20Sopenharmony_cinetwork. They are set on the device tree, but not used by the clock module. The
138c2ecf20Sopenharmony_cinetwork devices use them directly.
148c2ecf20Sopenharmony_ciExample can be found below.
158c2ecf20Sopenharmony_ci
168c2ecf20Sopenharmony_ciAll available clocks are defined as preprocessor macros in:
178c2ecf20Sopenharmony_cidt-bindings/clock/nuvoton,npcm7xx-clock.h
188c2ecf20Sopenharmony_ciand can be reused as DT sources.
198c2ecf20Sopenharmony_ci
208c2ecf20Sopenharmony_ciRequired Properties of clock controller:
218c2ecf20Sopenharmony_ci
228c2ecf20Sopenharmony_ci	- compatible: "nuvoton,npcm750-clk" : for clock controller of Nuvoton
238c2ecf20Sopenharmony_ci		  Poleg BMC NPCM750
248c2ecf20Sopenharmony_ci
258c2ecf20Sopenharmony_ci	- reg: physical base address of the clock controller and length of
268c2ecf20Sopenharmony_ci		memory mapped region.
278c2ecf20Sopenharmony_ci
288c2ecf20Sopenharmony_ci	- #clock-cells: should be 1.
298c2ecf20Sopenharmony_ci
308c2ecf20Sopenharmony_ciExample: Clock controller node:
318c2ecf20Sopenharmony_ci
328c2ecf20Sopenharmony_ci	clk: clock-controller@f0801000 {
338c2ecf20Sopenharmony_ci		compatible = "nuvoton,npcm750-clk";
348c2ecf20Sopenharmony_ci		#clock-cells = <1>;
358c2ecf20Sopenharmony_ci		reg = <0xf0801000 0x1000>;
368c2ecf20Sopenharmony_ci		clock-names = "refclk", "sysbypck", "mcbypck";
378c2ecf20Sopenharmony_ci		clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>;
388c2ecf20Sopenharmony_ci	};
398c2ecf20Sopenharmony_ci
408c2ecf20Sopenharmony_ciExample: Required external clocks for network:
418c2ecf20Sopenharmony_ci
428c2ecf20Sopenharmony_ci	/* external reference clock */
438c2ecf20Sopenharmony_ci	clk_refclk: clk-refclk {
448c2ecf20Sopenharmony_ci		compatible = "fixed-clock";
458c2ecf20Sopenharmony_ci		#clock-cells = <0>;
468c2ecf20Sopenharmony_ci		clock-frequency = <25000000>;
478c2ecf20Sopenharmony_ci		clock-output-names = "refclk";
488c2ecf20Sopenharmony_ci	};
498c2ecf20Sopenharmony_ci
508c2ecf20Sopenharmony_ci	/* external reference clock for cpu. float in normal operation */
518c2ecf20Sopenharmony_ci	clk_sysbypck: clk-sysbypck {
528c2ecf20Sopenharmony_ci		compatible = "fixed-clock";
538c2ecf20Sopenharmony_ci		#clock-cells = <0>;
548c2ecf20Sopenharmony_ci		clock-frequency = <800000000>;
558c2ecf20Sopenharmony_ci		clock-output-names = "sysbypck";
568c2ecf20Sopenharmony_ci	};
578c2ecf20Sopenharmony_ci
588c2ecf20Sopenharmony_ci	/* external reference clock for MC. float in normal operation */
598c2ecf20Sopenharmony_ci	clk_mcbypck: clk-mcbypck {
608c2ecf20Sopenharmony_ci		compatible = "fixed-clock";
618c2ecf20Sopenharmony_ci		#clock-cells = <0>;
628c2ecf20Sopenharmony_ci		clock-frequency = <800000000>;
638c2ecf20Sopenharmony_ci		clock-output-names = "mcbypck";
648c2ecf20Sopenharmony_ci	};
658c2ecf20Sopenharmony_ci
668c2ecf20Sopenharmony_ci	 /* external clock signal rg1refck, supplied by the phy */
678c2ecf20Sopenharmony_ci	clk_rg1refck: clk-rg1refck {
688c2ecf20Sopenharmony_ci		compatible = "fixed-clock";
698c2ecf20Sopenharmony_ci		#clock-cells = <0>;
708c2ecf20Sopenharmony_ci		clock-frequency = <125000000>;
718c2ecf20Sopenharmony_ci		clock-output-names = "clk_rg1refck";
728c2ecf20Sopenharmony_ci	};
738c2ecf20Sopenharmony_ci
748c2ecf20Sopenharmony_ci	 /* external clock signal rg2refck, supplied by the phy */
758c2ecf20Sopenharmony_ci	clk_rg2refck: clk-rg2refck {
768c2ecf20Sopenharmony_ci		compatible = "fixed-clock";
778c2ecf20Sopenharmony_ci		#clock-cells = <0>;
788c2ecf20Sopenharmony_ci		clock-frequency = <125000000>;
798c2ecf20Sopenharmony_ci		clock-output-names = "clk_rg2refck";
808c2ecf20Sopenharmony_ci	};
818c2ecf20Sopenharmony_ci
828c2ecf20Sopenharmony_ci	clk_xin: clk-xin {
838c2ecf20Sopenharmony_ci		compatible = "fixed-clock";
848c2ecf20Sopenharmony_ci		#clock-cells = <0>;
858c2ecf20Sopenharmony_ci		clock-frequency = <50000000>;
868c2ecf20Sopenharmony_ci		clock-output-names = "clk_xin";
878c2ecf20Sopenharmony_ci	};
888c2ecf20Sopenharmony_ci
898c2ecf20Sopenharmony_ci
908c2ecf20Sopenharmony_ciExample: GMAC controller node that consumes two clocks: a generated clk by the
918c2ecf20Sopenharmony_ciclock controller and a fixed clock from DT (clk_rg1refck).
928c2ecf20Sopenharmony_ci
938c2ecf20Sopenharmony_ci	ethernet0: ethernet@f0802000 {
948c2ecf20Sopenharmony_ci		compatible = "snps,dwmac";
958c2ecf20Sopenharmony_ci		reg = <0xf0802000 0x2000>;
968c2ecf20Sopenharmony_ci		interrupts = <0 14 4>;
978c2ecf20Sopenharmony_ci		interrupt-names = "macirq";
988c2ecf20Sopenharmony_ci		clocks	= <&clk_rg1refck>, <&clk NPCM7XX_CLK_AHB>;
998c2ecf20Sopenharmony_ci		clock-names = "stmmaceth", "clk_gmac";
1008c2ecf20Sopenharmony_ci	};
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