18c2ecf20Sopenharmony_ciDevice Tree Clock bindings for cpu clock of Marvell EBU platforms 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciRequired properties: 48c2ecf20Sopenharmony_ci- compatible : shall be one of the following: 58c2ecf20Sopenharmony_ci "marvell,armada-xp-cpu-clock" - cpu clocks for Armada XP 68c2ecf20Sopenharmony_ci "marvell,mv98dx3236-cpu-clock" - cpu clocks for 98DX3236 SoC 78c2ecf20Sopenharmony_ci- reg : Address and length of the clock complex register set, followed 88c2ecf20Sopenharmony_ci by address and length of the PMU DFS registers 98c2ecf20Sopenharmony_ci- #clock-cells : should be set to 1. 108c2ecf20Sopenharmony_ci- clocks : shall be the input parent clock phandle for the clock. 118c2ecf20Sopenharmony_ci 128c2ecf20Sopenharmony_cicpuclk: clock-complex@d0018700 { 138c2ecf20Sopenharmony_ci #clock-cells = <1>; 148c2ecf20Sopenharmony_ci compatible = "marvell,armada-xp-cpu-clock"; 158c2ecf20Sopenharmony_ci reg = <0xd0018700 0xA0>, <0x1c054 0x10>; 168c2ecf20Sopenharmony_ci clocks = <&coreclk 1>; 178c2ecf20Sopenharmony_ci} 188c2ecf20Sopenharmony_ci 198c2ecf20Sopenharmony_cicpu@0 { 208c2ecf20Sopenharmony_ci compatible = "marvell,sheeva-v7"; 218c2ecf20Sopenharmony_ci reg = <0>; 228c2ecf20Sopenharmony_ci clocks = <&cpuclk 0>; 238c2ecf20Sopenharmony_ci}; 24