18c2ecf20Sopenharmony_ci# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
28c2ecf20Sopenharmony_ci%YAML 1.2
38c2ecf20Sopenharmony_ci---
48c2ecf20Sopenharmony_ci$id: http://devicetree.org/schemas/clock/microchip,sparx5-dpll.yaml#
58c2ecf20Sopenharmony_ci$schema: http://devicetree.org/meta-schemas/core.yaml#
68c2ecf20Sopenharmony_ci
78c2ecf20Sopenharmony_cititle: Microchip Sparx5 DPLL Clock
88c2ecf20Sopenharmony_ci
98c2ecf20Sopenharmony_cimaintainers:
108c2ecf20Sopenharmony_ci  - Lars Povlsen <lars.povlsen@microchip.com>
118c2ecf20Sopenharmony_ci
128c2ecf20Sopenharmony_cidescription: |
138c2ecf20Sopenharmony_ci  The Sparx5 DPLL clock controller generates and supplies clock to
148c2ecf20Sopenharmony_ci  various peripherals within the SoC.
158c2ecf20Sopenharmony_ci
168c2ecf20Sopenharmony_ciproperties:
178c2ecf20Sopenharmony_ci  compatible:
188c2ecf20Sopenharmony_ci    const: microchip,sparx5-dpll
198c2ecf20Sopenharmony_ci
208c2ecf20Sopenharmony_ci  reg:
218c2ecf20Sopenharmony_ci    maxItems: 1
228c2ecf20Sopenharmony_ci
238c2ecf20Sopenharmony_ci  clocks:
248c2ecf20Sopenharmony_ci    maxItems: 1
258c2ecf20Sopenharmony_ci
268c2ecf20Sopenharmony_ci  '#clock-cells':
278c2ecf20Sopenharmony_ci    const: 1
288c2ecf20Sopenharmony_ci
298c2ecf20Sopenharmony_cirequired:
308c2ecf20Sopenharmony_ci  - compatible
318c2ecf20Sopenharmony_ci  - reg
328c2ecf20Sopenharmony_ci  - clocks
338c2ecf20Sopenharmony_ci  - '#clock-cells'
348c2ecf20Sopenharmony_ci
358c2ecf20Sopenharmony_ciadditionalProperties: false
368c2ecf20Sopenharmony_ci
378c2ecf20Sopenharmony_ciexamples:
388c2ecf20Sopenharmony_ci  # Clock provider for eMMC:
398c2ecf20Sopenharmony_ci  - |
408c2ecf20Sopenharmony_ci    lcpll_clk: lcpll-clk {
418c2ecf20Sopenharmony_ci        compatible = "fixed-clock";
428c2ecf20Sopenharmony_ci        #clock-cells = <0>;
438c2ecf20Sopenharmony_ci        clock-frequency = <2500000000>;
448c2ecf20Sopenharmony_ci    };
458c2ecf20Sopenharmony_ci    clks: clock-controller@61110000c {
468c2ecf20Sopenharmony_ci        compatible = "microchip,sparx5-dpll";
478c2ecf20Sopenharmony_ci        #clock-cells = <1>;
488c2ecf20Sopenharmony_ci        clocks = <&lcpll_clk>;
498c2ecf20Sopenharmony_ci        reg = <0x1110000c 0x24>;
508c2ecf20Sopenharmony_ci    };
518c2ecf20Sopenharmony_ci
528c2ecf20Sopenharmony_ci...
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