18c2ecf20Sopenharmony_ciDevicetree bindings for Maxim MAX9485 Programmable Audio Clock Generator
28c2ecf20Sopenharmony_ci
38c2ecf20Sopenharmony_ciThis device exposes 4 clocks in total:
48c2ecf20Sopenharmony_ci
58c2ecf20Sopenharmony_ci- MAX9485_MCLKOUT: 	A gated, buffered output of the input clock of 27 MHz
68c2ecf20Sopenharmony_ci- MAX9485_CLKOUT:	A PLL that can be configured to 16 different discrete
78c2ecf20Sopenharmony_ci			frequencies
88c2ecf20Sopenharmony_ci- MAX9485_CLKOUT[1,2]:	Two gated outputs for MAX9485_CLKOUT
98c2ecf20Sopenharmony_ci
108c2ecf20Sopenharmony_ciMAX9485_CLKOUT[1,2] are children of MAX9485_CLKOUT which upchain all rate set
118c2ecf20Sopenharmony_cirequests.
128c2ecf20Sopenharmony_ci
138c2ecf20Sopenharmony_ciRequired properties:
148c2ecf20Sopenharmony_ci- compatible:	"maxim,max9485"
158c2ecf20Sopenharmony_ci- clocks:	Input clock, must provice 27.000 MHz
168c2ecf20Sopenharmony_ci- clock-names:	Must be set to "xclk"
178c2ecf20Sopenharmony_ci- #clock-cells: From common clock binding; shall be set to 1
188c2ecf20Sopenharmony_ci
198c2ecf20Sopenharmony_ciOptional properties:
208c2ecf20Sopenharmony_ci- reset-gpios:		GPIO descriptor connected to the #RESET input pin
218c2ecf20Sopenharmony_ci- vdd-supply:		A regulator node for Vdd
228c2ecf20Sopenharmony_ci- clock-output-names:	Name of output clocks, as defined in common clock
238c2ecf20Sopenharmony_ci			bindings
248c2ecf20Sopenharmony_ci
258c2ecf20Sopenharmony_ciIf not explicitly set, the output names are "mclkout", "clkout", "clkout1"
268c2ecf20Sopenharmony_ciand "clkout2".
278c2ecf20Sopenharmony_ci
288c2ecf20Sopenharmony_ciClocks are defined as preprocessor macros in the dt-binding header.
298c2ecf20Sopenharmony_ci
308c2ecf20Sopenharmony_ciExample:
318c2ecf20Sopenharmony_ci
328c2ecf20Sopenharmony_ci	#include <dt-bindings/clock/maxim,max9485.h>
338c2ecf20Sopenharmony_ci
348c2ecf20Sopenharmony_ci	xo-27mhz: xo-27mhz {
358c2ecf20Sopenharmony_ci		compatible = "fixed-clock";
368c2ecf20Sopenharmony_ci		#clock-cells = <0>;
378c2ecf20Sopenharmony_ci		clock-frequency = <27000000>;
388c2ecf20Sopenharmony_ci	};
398c2ecf20Sopenharmony_ci
408c2ecf20Sopenharmony_ci	&i2c0 {
418c2ecf20Sopenharmony_ci		max9485: audio-clock@63 {
428c2ecf20Sopenharmony_ci			reg = <0x63>;
438c2ecf20Sopenharmony_ci			compatible = "maxim,max9485";
448c2ecf20Sopenharmony_ci			clock-names = "xclk";
458c2ecf20Sopenharmony_ci			clocks = <&xo-27mhz>;
468c2ecf20Sopenharmony_ci			reset-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
478c2ecf20Sopenharmony_ci			vdd-supply = <&3v3-reg>;
488c2ecf20Sopenharmony_ci			#clock-cells = <1>;
498c2ecf20Sopenharmony_ci		};
508c2ecf20Sopenharmony_ci	};
518c2ecf20Sopenharmony_ci
528c2ecf20Sopenharmony_ci	// Clock consumer node
538c2ecf20Sopenharmony_ci
548c2ecf20Sopenharmony_ci	foo@0 {
558c2ecf20Sopenharmony_ci		compatible = "bar,foo";
568c2ecf20Sopenharmony_ci		/* ... */
578c2ecf20Sopenharmony_ci		clock-names = "foo-input-clk";
588c2ecf20Sopenharmony_ci		clocks = <&max9485 MAX9485_CLKOUT1>;
598c2ecf20Sopenharmony_ci	};
60