18c2ecf20Sopenharmony_ci* Marvell PXA168 Clock Controller 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciThe PXA168 clock subsystem generates and supplies clock to various 48c2ecf20Sopenharmony_cicontrollers within the PXA168 SoC. 58c2ecf20Sopenharmony_ci 68c2ecf20Sopenharmony_ciRequired Properties: 78c2ecf20Sopenharmony_ci 88c2ecf20Sopenharmony_ci- compatible: should be one of the following. 98c2ecf20Sopenharmony_ci - "marvell,pxa168-clock" - controller compatible with PXA168 SoC. 108c2ecf20Sopenharmony_ci 118c2ecf20Sopenharmony_ci- reg: physical base address of the clock subsystem and length of memory mapped 128c2ecf20Sopenharmony_ci region. There are 3 places in SOC has clock control logic: 138c2ecf20Sopenharmony_ci "mpmu", "apmu", "apbc". So three reg spaces need to be defined. 148c2ecf20Sopenharmony_ci 158c2ecf20Sopenharmony_ci- #clock-cells: should be 1. 168c2ecf20Sopenharmony_ci- #reset-cells: should be 1. 178c2ecf20Sopenharmony_ci 188c2ecf20Sopenharmony_ciEach clock is assigned an identifier and client nodes use this identifier 198c2ecf20Sopenharmony_cito specify the clock which they consume. 208c2ecf20Sopenharmony_ci 218c2ecf20Sopenharmony_ciAll these identifier could be found in <dt-bindings/clock/marvell,pxa168.h>. 22