18c2ecf20Sopenharmony_ci# SPDX-License-Identifier: GPL-2.0
28c2ecf20Sopenharmony_ci%YAML 1.2
38c2ecf20Sopenharmony_ci---
48c2ecf20Sopenharmony_ci$id: http://devicetree.org/schemas/clock/marvell,mmp2-clock.yaml#
58c2ecf20Sopenharmony_ci$schema: http://devicetree.org/meta-schemas/core.yaml#
68c2ecf20Sopenharmony_ci
78c2ecf20Sopenharmony_cititle: Marvell MMP2 and MMP3 Clock Controller
88c2ecf20Sopenharmony_ci
98c2ecf20Sopenharmony_cimaintainers:
108c2ecf20Sopenharmony_ci  - Lubomir Rintel <lkundrak@v3.sk>
118c2ecf20Sopenharmony_ci
128c2ecf20Sopenharmony_cidescription: |
138c2ecf20Sopenharmony_ci  The clock subsystem on MMP2 or MMP3 generates and supplies clock to various
148c2ecf20Sopenharmony_ci  controllers within the SoC.
158c2ecf20Sopenharmony_ci
168c2ecf20Sopenharmony_ci  Each clock is assigned an identifier and client nodes use this identifier
178c2ecf20Sopenharmony_ci  to specify the clock which they consume.
188c2ecf20Sopenharmony_ci
198c2ecf20Sopenharmony_ci  All these identifiers could be found in <dt-bindings/clock/marvell,mmp2.h>.
208c2ecf20Sopenharmony_ci
218c2ecf20Sopenharmony_ciproperties:
228c2ecf20Sopenharmony_ci  compatible:
238c2ecf20Sopenharmony_ci    enum:
248c2ecf20Sopenharmony_ci      - marvell,mmp2-clock # controller compatible with MMP2 SoC
258c2ecf20Sopenharmony_ci      - marvell,mmp3-clock # controller compatible with MMP3 SoC
268c2ecf20Sopenharmony_ci
278c2ecf20Sopenharmony_ci  reg:
288c2ecf20Sopenharmony_ci    items:
298c2ecf20Sopenharmony_ci      - description: MPMU register region
308c2ecf20Sopenharmony_ci      - description: APMU register region
318c2ecf20Sopenharmony_ci      - description: APBC register region
328c2ecf20Sopenharmony_ci
338c2ecf20Sopenharmony_ci  reg-names:
348c2ecf20Sopenharmony_ci    items:
358c2ecf20Sopenharmony_ci      - const: mpmu
368c2ecf20Sopenharmony_ci      - const: apmu
378c2ecf20Sopenharmony_ci      - const: apbc
388c2ecf20Sopenharmony_ci
398c2ecf20Sopenharmony_ci  '#clock-cells':
408c2ecf20Sopenharmony_ci    const: 1
418c2ecf20Sopenharmony_ci
428c2ecf20Sopenharmony_ci  '#reset-cells':
438c2ecf20Sopenharmony_ci    const: 1
448c2ecf20Sopenharmony_ci
458c2ecf20Sopenharmony_ci  '#power-domain-cells':
468c2ecf20Sopenharmony_ci    const: 1
478c2ecf20Sopenharmony_ci
488c2ecf20Sopenharmony_cirequired:
498c2ecf20Sopenharmony_ci  - compatible
508c2ecf20Sopenharmony_ci  - reg
518c2ecf20Sopenharmony_ci  - reg-names
528c2ecf20Sopenharmony_ci  - '#clock-cells'
538c2ecf20Sopenharmony_ci  - '#reset-cells'
548c2ecf20Sopenharmony_ci  - '#power-domain-cells'
558c2ecf20Sopenharmony_ci
568c2ecf20Sopenharmony_ciadditionalProperties: false
578c2ecf20Sopenharmony_ci
588c2ecf20Sopenharmony_ciexamples:
598c2ecf20Sopenharmony_ci  - |
608c2ecf20Sopenharmony_ci    clock-controller@d4050000 {
618c2ecf20Sopenharmony_ci      compatible = "marvell,mmp2-clock";
628c2ecf20Sopenharmony_ci      reg = <0xd4050000 0x1000>,
638c2ecf20Sopenharmony_ci            <0xd4282800 0x400>,
648c2ecf20Sopenharmony_ci            <0xd4015000 0x1000>;
658c2ecf20Sopenharmony_ci      reg-names = "mpmu", "apmu", "apbc";
668c2ecf20Sopenharmony_ci      #clock-cells = <1>;
678c2ecf20Sopenharmony_ci      #reset-cells = <1>;
688c2ecf20Sopenharmony_ci      #power-domain-cells = <1>;
698c2ecf20Sopenharmony_ci    };
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