18c2ecf20Sopenharmony_ciDevice Tree Clock bindings for Marvell Berlin 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciThis binding uses the common clock binding[1]. 48c2ecf20Sopenharmony_ci 58c2ecf20Sopenharmony_ci[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 68c2ecf20Sopenharmony_ci 78c2ecf20Sopenharmony_ciClock related registers are spread among the chip control registers. Berlin 88c2ecf20Sopenharmony_ciclock node should be a sub-node of the chip controller node. Marvell Berlin2 98c2ecf20Sopenharmony_ci(BG2, BG2CD, BG2Q) SoCs share the same IP for PLLs and clocks, with some 108c2ecf20Sopenharmony_ciminor differences in features and register layout. 118c2ecf20Sopenharmony_ci 128c2ecf20Sopenharmony_ciRequired properties: 138c2ecf20Sopenharmony_ci- compatible: must be "marvell,berlin2-clk" or "marvell,berlin2q-clk" 148c2ecf20Sopenharmony_ci- #clock-cells: must be 1 158c2ecf20Sopenharmony_ci- clocks: must be the input parent clock phandle 168c2ecf20Sopenharmony_ci- clock-names: name of the input parent clock 178c2ecf20Sopenharmony_ci Allowed clock-names for the reference clocks are 188c2ecf20Sopenharmony_ci "refclk" for the SoCs oscillator input on all SoCs, 198c2ecf20Sopenharmony_ci and SoC-specific input clocks for 208c2ecf20Sopenharmony_ci BG2/BG2CD: "video_ext0" for the external video clock input 218c2ecf20Sopenharmony_ci 228c2ecf20Sopenharmony_ci 238c2ecf20Sopenharmony_ciExample: 248c2ecf20Sopenharmony_ci 258c2ecf20Sopenharmony_cichip_clk: clock { 268c2ecf20Sopenharmony_ci compatible = "marvell,berlin2q-clk"; 278c2ecf20Sopenharmony_ci 288c2ecf20Sopenharmony_ci #clock-cells = <1>; 298c2ecf20Sopenharmony_ci clocks = <&refclk>; 308c2ecf20Sopenharmony_ci clock-names = "refclk"; 318c2ecf20Sopenharmony_ci}; 32