18c2ecf20Sopenharmony_ciDevice Tree Clock bindings for Intel's SoCFPGA Stratix10 platform 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciThis binding uses the common clock binding[1]. 48c2ecf20Sopenharmony_ci 58c2ecf20Sopenharmony_ci[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 68c2ecf20Sopenharmony_ci 78c2ecf20Sopenharmony_ciRequired properties: 88c2ecf20Sopenharmony_ci- compatible : shall be 98c2ecf20Sopenharmony_ci "intel,stratix10-clkmgr" 108c2ecf20Sopenharmony_ci 118c2ecf20Sopenharmony_ci- reg : shall be the control register offset from CLOCK_MANAGER's base for the clock. 128c2ecf20Sopenharmony_ci 138c2ecf20Sopenharmony_ci- #clock-cells : from common clock binding, shall be set to 1. 148c2ecf20Sopenharmony_ci 158c2ecf20Sopenharmony_ciExample: 168c2ecf20Sopenharmony_ci clkmgr: clock-controller@ffd10000 { 178c2ecf20Sopenharmony_ci compatible = "intel,stratix10-clkmgr"; 188c2ecf20Sopenharmony_ci reg = <0xffd10000 0x1000>; 198c2ecf20Sopenharmony_ci #clock-cells = <1>; 208c2ecf20Sopenharmony_ci }; 21