18c2ecf20Sopenharmony_ciBinding for simple memory mapped io fixed-rate clock sources. 28c2ecf20Sopenharmony_ciThe driver reads a clock frequency value from a single 32-bit memory mapped 38c2ecf20Sopenharmony_ciI/O register and registers it as a fixed rate clock. 48c2ecf20Sopenharmony_ci 58c2ecf20Sopenharmony_ciIt was designed for test systems, like FPGA, not for complete, finished SoCs. 68c2ecf20Sopenharmony_ci 78c2ecf20Sopenharmony_ciThis binding uses the common clock binding[1]. 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_ci[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 108c2ecf20Sopenharmony_ci 118c2ecf20Sopenharmony_ciRequired properties: 128c2ecf20Sopenharmony_ci- compatible : shall be "fixed-mmio-clock". 138c2ecf20Sopenharmony_ci- #clock-cells : from common clock binding; shall be set to 0. 148c2ecf20Sopenharmony_ci- reg : Address and length of the clock value register set. 158c2ecf20Sopenharmony_ci 168c2ecf20Sopenharmony_ciOptional properties: 178c2ecf20Sopenharmony_ci- clock-output-names : From common clock binding. 188c2ecf20Sopenharmony_ci 198c2ecf20Sopenharmony_ciExample: 208c2ecf20Sopenharmony_cisysclock: sysclock@fd020004 { 218c2ecf20Sopenharmony_ci #clock-cells = <0>; 228c2ecf20Sopenharmony_ci compatible = "fixed-mmio-clock"; 238c2ecf20Sopenharmony_ci reg = <0xfd020004 0x4>; 248c2ecf20Sopenharmony_ci}; 25