18c2ecf20Sopenharmony_ci* Samsung Exynos5410 Clock Controller 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciThe Exynos5410 clock controller generates and supplies clock to various 48c2ecf20Sopenharmony_cicontrollers within the Exynos5410 SoC. 58c2ecf20Sopenharmony_ci 68c2ecf20Sopenharmony_ciRequired Properties: 78c2ecf20Sopenharmony_ci 88c2ecf20Sopenharmony_ci- compatible: should be "samsung,exynos5410-clock" 98c2ecf20Sopenharmony_ci 108c2ecf20Sopenharmony_ci- reg: physical base address of the controller and length of memory mapped 118c2ecf20Sopenharmony_ci region. 128c2ecf20Sopenharmony_ci 138c2ecf20Sopenharmony_ci- #clock-cells: should be 1. 148c2ecf20Sopenharmony_ci 158c2ecf20Sopenharmony_ci- clocks: should contain an entry specifying the root clock from external 168c2ecf20Sopenharmony_ci oscillator supplied through XXTI or XusbXTI pin. This clock should be 178c2ecf20Sopenharmony_ci defined using standard clock bindings with "fin_pll" clock-output-name. 188c2ecf20Sopenharmony_ci That clock is being passed internally to the 9 PLLs. 198c2ecf20Sopenharmony_ci 208c2ecf20Sopenharmony_ciAll available clocks are defined as preprocessor macros in 218c2ecf20Sopenharmony_cidt-bindings/clock/exynos5410.h header and can be used in device 228c2ecf20Sopenharmony_citree sources. 238c2ecf20Sopenharmony_ci 248c2ecf20Sopenharmony_ciExample 1: An example of a clock controller node is listed below. 258c2ecf20Sopenharmony_ci 268c2ecf20Sopenharmony_ci fin_pll: xxti { 278c2ecf20Sopenharmony_ci compatible = "fixed-clock"; 288c2ecf20Sopenharmony_ci clock-frequency = <24000000>; 298c2ecf20Sopenharmony_ci clock-output-names = "fin_pll"; 308c2ecf20Sopenharmony_ci #clock-cells = <0>; 318c2ecf20Sopenharmony_ci }; 328c2ecf20Sopenharmony_ci 338c2ecf20Sopenharmony_ci clock: clock-controller@10010000 { 348c2ecf20Sopenharmony_ci compatible = "samsung,exynos5410-clock"; 358c2ecf20Sopenharmony_ci reg = <0x10010000 0x30000>; 368c2ecf20Sopenharmony_ci #clock-cells = <1>; 378c2ecf20Sopenharmony_ci clocks = <&fin_pll>; 388c2ecf20Sopenharmony_ci }; 398c2ecf20Sopenharmony_ci 408c2ecf20Sopenharmony_ciExample 2: UART controller node that consumes the clock generated by the clock 418c2ecf20Sopenharmony_ci controller. Refer to the standard clock bindings for information 428c2ecf20Sopenharmony_ci about 'clocks' and 'clock-names' property. 438c2ecf20Sopenharmony_ci 448c2ecf20Sopenharmony_ci serial@12c20000 { 458c2ecf20Sopenharmony_ci compatible = "samsung,exynos4210-uart"; 468c2ecf20Sopenharmony_ci reg = <0x12C00000 0x100>; 478c2ecf20Sopenharmony_ci interrupts = <0 51 0>; 488c2ecf20Sopenharmony_ci clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; 498c2ecf20Sopenharmony_ci clock-names = "uart", "clk_uart_baud0"; 508c2ecf20Sopenharmony_ci }; 51