18c2ecf20Sopenharmony_ci* Samsung Exynos3250 Clock Controller
28c2ecf20Sopenharmony_ci
38c2ecf20Sopenharmony_ciThe Exynos3250 clock controller generates and supplies clock to various
48c2ecf20Sopenharmony_cicontrollers within the Exynos3250 SoC.
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68c2ecf20Sopenharmony_ciRequired Properties:
78c2ecf20Sopenharmony_ci
88c2ecf20Sopenharmony_ci- compatible: should be one of the following.
98c2ecf20Sopenharmony_ci  - "samsung,exynos3250-cmu" - controller compatible with Exynos3250 SoC.
108c2ecf20Sopenharmony_ci  - "samsung,exynos3250-cmu-dmc" - controller compatible with
118c2ecf20Sopenharmony_ci    Exynos3250 SoC for Dynamic Memory Controller domain.
128c2ecf20Sopenharmony_ci  - "samsung,exynos3250-cmu-isp" - ISP block clock controller compatible
138c2ecf20Sopenharmony_ci     with Exynos3250 SOC
148c2ecf20Sopenharmony_ci
158c2ecf20Sopenharmony_ci- reg: physical base address of the controller and length of memory mapped
168c2ecf20Sopenharmony_ci  region.
178c2ecf20Sopenharmony_ci
188c2ecf20Sopenharmony_ci- #clock-cells: should be 1.
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208c2ecf20Sopenharmony_ciEach clock is assigned an identifier and client nodes can use this identifier
218c2ecf20Sopenharmony_cito specify the clock which they consume.
228c2ecf20Sopenharmony_ci
238c2ecf20Sopenharmony_ciAll available clocks are defined as preprocessor macros in
248c2ecf20Sopenharmony_cidt-bindings/clock/exynos3250.h header and can be used in device
258c2ecf20Sopenharmony_citree sources.
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278c2ecf20Sopenharmony_ciExample 1: Examples of clock controller nodes are listed below.
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298c2ecf20Sopenharmony_ci	cmu: clock-controller@10030000 {
308c2ecf20Sopenharmony_ci		compatible = "samsung,exynos3250-cmu";
318c2ecf20Sopenharmony_ci		reg = <0x10030000 0x20000>;
328c2ecf20Sopenharmony_ci		#clock-cells = <1>;
338c2ecf20Sopenharmony_ci	};
348c2ecf20Sopenharmony_ci
358c2ecf20Sopenharmony_ci	cmu_dmc: clock-controller@105c0000 {
368c2ecf20Sopenharmony_ci		compatible = "samsung,exynos3250-cmu-dmc";
378c2ecf20Sopenharmony_ci		reg = <0x105C0000 0x2000>;
388c2ecf20Sopenharmony_ci		#clock-cells = <1>;
398c2ecf20Sopenharmony_ci	};
408c2ecf20Sopenharmony_ci
418c2ecf20Sopenharmony_ci	cmu_isp: clock-controller@10048000 {
428c2ecf20Sopenharmony_ci		compatible = "samsung,exynos3250-cmu-isp";
438c2ecf20Sopenharmony_ci		reg = <0x10048000 0x1000>;
448c2ecf20Sopenharmony_ci		#clock-cells = <1>;
458c2ecf20Sopenharmony_ci	};
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478c2ecf20Sopenharmony_ciExample 2: UART controller node that consumes the clock generated by the clock
488c2ecf20Sopenharmony_ci	   controller. Refer to the standard clock bindings for information
498c2ecf20Sopenharmony_ci	   about 'clocks' and 'clock-names' property.
508c2ecf20Sopenharmony_ci
518c2ecf20Sopenharmony_ci	serial@13800000 {
528c2ecf20Sopenharmony_ci		compatible = "samsung,exynos4210-uart";
538c2ecf20Sopenharmony_ci		reg = <0x13800000 0x100>;
548c2ecf20Sopenharmony_ci		interrupts = <0 109 0>;
558c2ecf20Sopenharmony_ci		clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
568c2ecf20Sopenharmony_ci		clock-names = "uart", "clk_uart_baud0";
578c2ecf20Sopenharmony_ci	};
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