18c2ecf20Sopenharmony_ciPLL divider based Dove clocks 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciMarvell Dove has a 2GHz PLL, which feeds into a set of dividers to provide 48c2ecf20Sopenharmony_cihigh speed clocks for a number of peripherals. These dividers are part of 58c2ecf20Sopenharmony_cithe PMU, and thus this node should be a child of the PMU node. 68c2ecf20Sopenharmony_ci 78c2ecf20Sopenharmony_ciThe following clocks are provided: 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_ciID Clock 108c2ecf20Sopenharmony_ci------------- 118c2ecf20Sopenharmony_ci0 AXI bus clock 128c2ecf20Sopenharmony_ci1 GPU clock 138c2ecf20Sopenharmony_ci2 VMeta clock 148c2ecf20Sopenharmony_ci3 LCD clock 158c2ecf20Sopenharmony_ci 168c2ecf20Sopenharmony_ciRequired properties: 178c2ecf20Sopenharmony_ci- compatible : shall be "marvell,dove-divider-clock" 188c2ecf20Sopenharmony_ci- reg : shall be the register address of the Core PLL and Clock Divider 198c2ecf20Sopenharmony_ci Control 0 register. This will cover that register, as well as the 208c2ecf20Sopenharmony_ci Core PLL and Clock Divider Control 1 register. Thus, it will have 218c2ecf20Sopenharmony_ci a size of 8. 228c2ecf20Sopenharmony_ci- #clock-cells : from common clock binding; shall be set to 1 238c2ecf20Sopenharmony_ci 248c2ecf20Sopenharmony_cidivider_clk: core-clock@64 { 258c2ecf20Sopenharmony_ci compatible = "marvell,dove-divider-clock"; 268c2ecf20Sopenharmony_ci reg = <0x0064 0x8>; 278c2ecf20Sopenharmony_ci #clock-cells = <1>; 288c2ecf20Sopenharmony_ci}; 29