18c2ecf20Sopenharmony_ci* Clock and reset bindings for CSR atlas7
28c2ecf20Sopenharmony_ci
38c2ecf20Sopenharmony_ciRequired properties:
48c2ecf20Sopenharmony_ci- compatible: Should be "sirf,atlas7-car"
58c2ecf20Sopenharmony_ci- reg: Address and length of the register set
68c2ecf20Sopenharmony_ci- #clock-cells: Should be <1>
78c2ecf20Sopenharmony_ci- #reset-cells: Should be <1>
88c2ecf20Sopenharmony_ci
98c2ecf20Sopenharmony_ciThe clock consumer should specify the desired clock by having the clock
108c2ecf20Sopenharmony_ciID in its "clocks" phandle cell.
118c2ecf20Sopenharmony_ciThe ID list atlas7_clks defined in drivers/clk/sirf/clk-atlas7.c
128c2ecf20Sopenharmony_ci
138c2ecf20Sopenharmony_ciThe reset consumer should specify the desired reset by having the reset
148c2ecf20Sopenharmony_ciID in its "reset" phandle cell.
158c2ecf20Sopenharmony_ciThe ID list atlas7_reset_unit defined in drivers/clk/sirf/clk-atlas7.c
168c2ecf20Sopenharmony_ci
178c2ecf20Sopenharmony_ciExamples: Clock and reset controller node:
188c2ecf20Sopenharmony_ci
198c2ecf20Sopenharmony_cicar: clock-controller@18620000 {
208c2ecf20Sopenharmony_ci	compatible = "sirf,atlas7-car";
218c2ecf20Sopenharmony_ci	reg = <0x18620000 0x1000>;
228c2ecf20Sopenharmony_ci	#clock-cells = <1>;
238c2ecf20Sopenharmony_ci	#reset-cells = <1>;
248c2ecf20Sopenharmony_ci};
258c2ecf20Sopenharmony_ci
268c2ecf20Sopenharmony_ciExamples: Consumers using clock or reset:
278c2ecf20Sopenharmony_ci
288c2ecf20Sopenharmony_citimer@10dc0000 {
298c2ecf20Sopenharmony_ci	compatible = "sirf,macro-tick";
308c2ecf20Sopenharmony_ci	reg = <0x10dc0000 0x1000>;
318c2ecf20Sopenharmony_ci	clocks = <&car 54>;
328c2ecf20Sopenharmony_ci	interrupts = <0 0 0>,
338c2ecf20Sopenharmony_ci		   <0 1 0>,
348c2ecf20Sopenharmony_ci		   <0 2 0>,
358c2ecf20Sopenharmony_ci		   <0 49 0>,
368c2ecf20Sopenharmony_ci		   <0 50 0>,
378c2ecf20Sopenharmony_ci		   <0 51 0>;
388c2ecf20Sopenharmony_ci};
398c2ecf20Sopenharmony_ci
408c2ecf20Sopenharmony_ciuart1: uart@18020000 {
418c2ecf20Sopenharmony_ci	cell-index = <1>;
428c2ecf20Sopenharmony_ci	compatible = "sirf,macro-uart";
438c2ecf20Sopenharmony_ci	reg = <0x18020000 0x1000>;
448c2ecf20Sopenharmony_ci	clocks = <&clks 95>;
458c2ecf20Sopenharmony_ci	interrupts = <0 18 0>;
468c2ecf20Sopenharmony_ci	fifosize = <32>;
478c2ecf20Sopenharmony_ci};
488c2ecf20Sopenharmony_ci
498c2ecf20Sopenharmony_civpp@13110000 {
508c2ecf20Sopenharmony_ci	compatible = "sirf,prima2-vpp";
518c2ecf20Sopenharmony_ci	reg = <0x13110000 0x10000>;
528c2ecf20Sopenharmony_ci	interrupts = <0 31 0>;
538c2ecf20Sopenharmony_ci	clocks = <&car 85>;
548c2ecf20Sopenharmony_ci	resets = <&car 29>;
558c2ecf20Sopenharmony_ci};
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