18c2ecf20Sopenharmony_ci* Samsung Audio Subsystem Clock Controller 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciThe Samsung Audio Subsystem clock controller generates and supplies clocks 48c2ecf20Sopenharmony_cito Audio Subsystem block available in the S5PV210 and compatible SoCs. 58c2ecf20Sopenharmony_ci 68c2ecf20Sopenharmony_ciRequired Properties: 78c2ecf20Sopenharmony_ci 88c2ecf20Sopenharmony_ci- compatible: should be "samsung,s5pv210-audss-clock". 98c2ecf20Sopenharmony_ci- reg: physical base address and length of the controller's register set. 108c2ecf20Sopenharmony_ci 118c2ecf20Sopenharmony_ci- #clock-cells: should be 1. 128c2ecf20Sopenharmony_ci 138c2ecf20Sopenharmony_ci- clocks: 148c2ecf20Sopenharmony_ci - hclk: AHB bus clock of the Audio Subsystem. 158c2ecf20Sopenharmony_ci - xxti: Optional fixed rate PLL reference clock, parent of mout_audss. If 168c2ecf20Sopenharmony_ci not specified (i.e. xusbxti is used for PLL reference), it is fixed to 178c2ecf20Sopenharmony_ci a clock named "xxti". 188c2ecf20Sopenharmony_ci - fout_epll: Input PLL to the AudioSS block, parent of mout_audss. 198c2ecf20Sopenharmony_ci - iiscdclk0: Optional external i2s clock, parent of mout_i2s. If not 208c2ecf20Sopenharmony_ci specified, it is fixed to a clock named "iiscdclk0". 218c2ecf20Sopenharmony_ci - sclk_audio0: Audio bus clock, parent of mout_i2s. 228c2ecf20Sopenharmony_ci 238c2ecf20Sopenharmony_ci- clock-names: Aliases for the above clocks. They should be "hclk", 248c2ecf20Sopenharmony_ci "xxti", "fout_epll", "iiscdclk0", and "sclk_audio0" respectively. 258c2ecf20Sopenharmony_ci 268c2ecf20Sopenharmony_ciAll available clocks are defined as preprocessor macros in 278c2ecf20Sopenharmony_cidt-bindings/clock/s5pv210-audss-clk.h header and can be used in device 288c2ecf20Sopenharmony_citree sources. 298c2ecf20Sopenharmony_ci 308c2ecf20Sopenharmony_ciExample: Clock controller node. 318c2ecf20Sopenharmony_ci 328c2ecf20Sopenharmony_ci clk_audss: clock-controller@c0900000 { 338c2ecf20Sopenharmony_ci compatible = "samsung,s5pv210-audss-clock"; 348c2ecf20Sopenharmony_ci reg = <0xc0900000 0x1000>; 358c2ecf20Sopenharmony_ci #clock-cells = <1>; 368c2ecf20Sopenharmony_ci clock-names = "hclk", "xxti", 378c2ecf20Sopenharmony_ci "fout_epll", "sclk_audio0"; 388c2ecf20Sopenharmony_ci clocks = <&clocks DOUT_HCLKP>, <&xxti>, 398c2ecf20Sopenharmony_ci <&clocks FOUT_EPLL>, <&clocks SCLK_AUDIO0>; 408c2ecf20Sopenharmony_ci }; 418c2ecf20Sopenharmony_ci 428c2ecf20Sopenharmony_ciExample: I2S controller node that consumes the clock generated by the clock 438c2ecf20Sopenharmony_ci controller. Refer to the standard clock bindings for information 448c2ecf20Sopenharmony_ci about 'clocks' and 'clock-names' property. 458c2ecf20Sopenharmony_ci 468c2ecf20Sopenharmony_ci i2s0: i2s@3830000 { 478c2ecf20Sopenharmony_ci /* ... */ 488c2ecf20Sopenharmony_ci clock-names = "iis", "i2s_opclk0", 498c2ecf20Sopenharmony_ci "i2s_opclk1"; 508c2ecf20Sopenharmony_ci clocks = <&clk_audss CLK_I2S>, <&clk_audss CLK_I2S>, 518c2ecf20Sopenharmony_ci <&clk_audss CLK_DOUT_AUD_BUS>; 528c2ecf20Sopenharmony_ci /* ... */ 538c2ecf20Sopenharmony_ci }; 54