18c2ecf20Sopenharmony_ciBinding for the AXS10X I2S PLL clock 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciThis binding uses the common clock binding[1]. 48c2ecf20Sopenharmony_ci 58c2ecf20Sopenharmony_ci[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 68c2ecf20Sopenharmony_ci 78c2ecf20Sopenharmony_ciRequired properties: 88c2ecf20Sopenharmony_ci- compatible: shall be "snps,axs10x-i2s-pll-clock" 98c2ecf20Sopenharmony_ci- reg : address and length of the I2S PLL register set. 108c2ecf20Sopenharmony_ci- clocks: shall be the input parent clock phandle for the PLL. 118c2ecf20Sopenharmony_ci- #clock-cells: from common clock binding; Should always be set to 0. 128c2ecf20Sopenharmony_ci 138c2ecf20Sopenharmony_ciExample: 148c2ecf20Sopenharmony_ci pll_clock: pll_clock { 158c2ecf20Sopenharmony_ci compatible = "fixed-clock"; 168c2ecf20Sopenharmony_ci clock-frequency = <27000000>; 178c2ecf20Sopenharmony_ci #clock-cells = <0>; 188c2ecf20Sopenharmony_ci }; 198c2ecf20Sopenharmony_ci 208c2ecf20Sopenharmony_ci i2s_clock@100a0 { 218c2ecf20Sopenharmony_ci compatible = "snps,axs10x-i2s-pll-clock"; 228c2ecf20Sopenharmony_ci reg = <0x100a0 0x10>; 238c2ecf20Sopenharmony_ci clocks = <&pll_clock>; 248c2ecf20Sopenharmony_ci #clock-cells = <0>; 258c2ecf20Sopenharmony_ci }; 26