18c2ecf20Sopenharmony_ciBinding for the axi-clkgen clock generator 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciThis binding uses the common clock binding[1]. 48c2ecf20Sopenharmony_ci 58c2ecf20Sopenharmony_ci[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 68c2ecf20Sopenharmony_ci 78c2ecf20Sopenharmony_ciRequired properties: 88c2ecf20Sopenharmony_ci- compatible : shall be "adi,axi-clkgen-1.00.a" or "adi,axi-clkgen-2.00.a". 98c2ecf20Sopenharmony_ci- #clock-cells : from common clock binding; Should always be set to 0. 108c2ecf20Sopenharmony_ci- reg : Address and length of the axi-clkgen register set. 118c2ecf20Sopenharmony_ci- clocks : Phandle and clock specifier for the parent clock(s). This must 128c2ecf20Sopenharmony_ci either reference one clock if only the first clock input is connected or two 138c2ecf20Sopenharmony_ci if both clock inputs are connected. For the later case the clock connected 148c2ecf20Sopenharmony_ci to the first input must be specified first. 158c2ecf20Sopenharmony_ci 168c2ecf20Sopenharmony_ciOptional properties: 178c2ecf20Sopenharmony_ci- clock-output-names : From common clock binding. 188c2ecf20Sopenharmony_ci 198c2ecf20Sopenharmony_ciExample: 208c2ecf20Sopenharmony_ci clock@ff000000 { 218c2ecf20Sopenharmony_ci compatible = "adi,axi-clkgen"; 228c2ecf20Sopenharmony_ci #clock-cells = <0>; 238c2ecf20Sopenharmony_ci reg = <0xff000000 0x1000>; 248c2ecf20Sopenharmony_ci clocks = <&osc 1>; 258c2ecf20Sopenharmony_ci }; 26