18c2ecf20Sopenharmony_ciDevice Tree Clock bindings for arch-at91
28c2ecf20Sopenharmony_ci
38c2ecf20Sopenharmony_ciThis binding uses the common clock binding[1].
48c2ecf20Sopenharmony_ci
58c2ecf20Sopenharmony_ci[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
68c2ecf20Sopenharmony_ci
78c2ecf20Sopenharmony_ciSlow Clock controller:
88c2ecf20Sopenharmony_ci
98c2ecf20Sopenharmony_ciRequired properties:
108c2ecf20Sopenharmony_ci- compatible : shall be one of the following:
118c2ecf20Sopenharmony_ci	"atmel,at91sam9x5-sckc",
128c2ecf20Sopenharmony_ci	"atmel,sama5d3-sckc",
138c2ecf20Sopenharmony_ci	"atmel,sama5d4-sckc" or
148c2ecf20Sopenharmony_ci	"microchip,sam9x60-sckc":
158c2ecf20Sopenharmony_ci		at91 SCKC (Slow Clock Controller)
168c2ecf20Sopenharmony_ci- #clock-cells : shall be 1 for "microchip,sam9x60-sckc" otherwise shall be 0.
178c2ecf20Sopenharmony_ci- clocks : shall be the input parent clock phandle for the clock.
188c2ecf20Sopenharmony_ci
198c2ecf20Sopenharmony_ciOptional properties:
208c2ecf20Sopenharmony_ci- atmel,osc-bypass : boolean property. Set this when a clock signal is directly
218c2ecf20Sopenharmony_ci  provided on XIN.
228c2ecf20Sopenharmony_ci
238c2ecf20Sopenharmony_ciFor example:
248c2ecf20Sopenharmony_ci	sckc@fffffe50 {
258c2ecf20Sopenharmony_ci		compatible = "atmel,at91sam9x5-sckc";
268c2ecf20Sopenharmony_ci		reg = <0xfffffe50 0x4>;
278c2ecf20Sopenharmony_ci		clocks = <&slow_xtal>;
288c2ecf20Sopenharmony_ci		#clock-cells = <0>;
298c2ecf20Sopenharmony_ci	};
308c2ecf20Sopenharmony_ci
318c2ecf20Sopenharmony_ciPower Management Controller (PMC):
328c2ecf20Sopenharmony_ci
338c2ecf20Sopenharmony_ciRequired properties:
348c2ecf20Sopenharmony_ci- compatible : shall be "atmel,<chip>-pmc", "syscon" or
358c2ecf20Sopenharmony_ci	"microchip,sam9x60-pmc"
368c2ecf20Sopenharmony_ci	<chip> can be: at91rm9200, at91sam9260, at91sam9261,
378c2ecf20Sopenharmony_ci	at91sam9263, at91sam9g45, at91sam9n12, at91sam9rl, at91sam9g15,
388c2ecf20Sopenharmony_ci	at91sam9g25, at91sam9g35, at91sam9x25, at91sam9x35, at91sam9x5,
398c2ecf20Sopenharmony_ci	sama5d2, sama5d3 or sama5d4.
408c2ecf20Sopenharmony_ci- #clock-cells : from common clock binding; shall be set to 2. The first entry
418c2ecf20Sopenharmony_ci  is the type of the clock (core, system, peripheral or generated) and the
428c2ecf20Sopenharmony_ci  second entry its index as provided by the datasheet
438c2ecf20Sopenharmony_ci- clocks : Must contain an entry for each entry in clock-names.
448c2ecf20Sopenharmony_ci- clock-names: Must include the following entries: "slow_clk", "main_xtal"
458c2ecf20Sopenharmony_ci
468c2ecf20Sopenharmony_ciOptional properties:
478c2ecf20Sopenharmony_ci- atmel,osc-bypass : boolean property. Set this when a clock signal is directly
488c2ecf20Sopenharmony_ci  provided on XIN.
498c2ecf20Sopenharmony_ci
508c2ecf20Sopenharmony_ciFor example:
518c2ecf20Sopenharmony_ci	pmc: pmc@f0018000 {
528c2ecf20Sopenharmony_ci		compatible = "atmel,sama5d4-pmc", "syscon";
538c2ecf20Sopenharmony_ci		reg = <0xf0018000 0x120>;
548c2ecf20Sopenharmony_ci		interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
558c2ecf20Sopenharmony_ci		#clock-cells = <2>;
568c2ecf20Sopenharmony_ci		clocks = <&clk32k>, <&main_xtal>;
578c2ecf20Sopenharmony_ci		clock-names = "slow_clk", "main_xtal";
588c2ecf20Sopenharmony_ci	};
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