18c2ecf20Sopenharmony_ci* Amlogic GXBB AO Clock and Reset Unit 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciThe Amlogic GXBB AO clock controller generates and supplies clock to various 48c2ecf20Sopenharmony_cicontrollers within the Always-On part of the SoC. 58c2ecf20Sopenharmony_ci 68c2ecf20Sopenharmony_ciRequired Properties: 78c2ecf20Sopenharmony_ci 88c2ecf20Sopenharmony_ci- compatible: value should be different for each SoC family as : 98c2ecf20Sopenharmony_ci - GXBB (S905) : "amlogic,meson-gxbb-aoclkc" 108c2ecf20Sopenharmony_ci - GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc" 118c2ecf20Sopenharmony_ci - GXM (S912) : "amlogic,meson-gxm-aoclkc" 128c2ecf20Sopenharmony_ci - AXG (A113D, A113X) : "amlogic,meson-axg-aoclkc" 138c2ecf20Sopenharmony_ci - G12A (S905X2, S905D2, S905Y2) : "amlogic,meson-g12a-aoclkc" 148c2ecf20Sopenharmony_ci followed by the common "amlogic,meson-gx-aoclkc" 158c2ecf20Sopenharmony_ci- clocks: list of clock phandle, one for each entry clock-names. 168c2ecf20Sopenharmony_ci- clock-names: should contain the following: 178c2ecf20Sopenharmony_ci * "xtal" : the platform xtal 188c2ecf20Sopenharmony_ci * "mpeg-clk" : the main clock controller mother clock (aka clk81) 198c2ecf20Sopenharmony_ci * "ext-32k-0" : external 32kHz reference #0 if any (optional) 208c2ecf20Sopenharmony_ci * "ext-32k-1" : external 32kHz reference #1 if any (optional - gx only) 218c2ecf20Sopenharmony_ci * "ext-32k-2" : external 32kHz reference #2 if any (optional - gx only) 228c2ecf20Sopenharmony_ci 238c2ecf20Sopenharmony_ci- #clock-cells: should be 1. 248c2ecf20Sopenharmony_ci 258c2ecf20Sopenharmony_ciEach clock is assigned an identifier and client nodes can use this identifier 268c2ecf20Sopenharmony_cito specify the clock which they consume. All available clocks are defined as 278c2ecf20Sopenharmony_cipreprocessor macros in the dt-bindings/clock/gxbb-aoclkc.h header and can be 288c2ecf20Sopenharmony_ciused in device tree sources. 298c2ecf20Sopenharmony_ci 308c2ecf20Sopenharmony_ci- #reset-cells: should be 1. 318c2ecf20Sopenharmony_ci 328c2ecf20Sopenharmony_ciEach reset is assigned an identifier and client nodes can use this identifier 338c2ecf20Sopenharmony_cito specify the reset which they consume. All available resets are defined as 348c2ecf20Sopenharmony_cipreprocessor macros in the dt-bindings/reset/gxbb-aoclkc.h header and can be 358c2ecf20Sopenharmony_ciused in device tree sources. 368c2ecf20Sopenharmony_ci 378c2ecf20Sopenharmony_ciParent node should have the following properties : 388c2ecf20Sopenharmony_ci- compatible: "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd" 398c2ecf20Sopenharmony_ci- reg: base address and size of the AO system control register space. 408c2ecf20Sopenharmony_ci 418c2ecf20Sopenharmony_ciExample: AO Clock controller node: 428c2ecf20Sopenharmony_ci 438c2ecf20Sopenharmony_ciao_sysctrl: sys-ctrl@0 { 448c2ecf20Sopenharmony_ci compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd"; 458c2ecf20Sopenharmony_ci reg = <0x0 0x0 0x0 0x100>; 468c2ecf20Sopenharmony_ci 478c2ecf20Sopenharmony_ci clkc_AO: clock-controller { 488c2ecf20Sopenharmony_ci compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc"; 498c2ecf20Sopenharmony_ci #clock-cells = <1>; 508c2ecf20Sopenharmony_ci #reset-cells = <1>; 518c2ecf20Sopenharmony_ci clocks = <&xtal>, <&clkc CLKID_CLK81>; 528c2ecf20Sopenharmony_ci clock-names = "xtal", "mpeg-clk"; 538c2ecf20Sopenharmony_ci }; 548c2ecf20Sopenharmony_ci 558c2ecf20Sopenharmony_ciExample: UART controller node that consumes the clock and reset generated 568c2ecf20Sopenharmony_ci by the clock controller: 578c2ecf20Sopenharmony_ci 588c2ecf20Sopenharmony_ci uart_AO: serial@4c0 { 598c2ecf20Sopenharmony_ci compatible = "amlogic,meson-uart"; 608c2ecf20Sopenharmony_ci reg = <0x4c0 0x14>; 618c2ecf20Sopenharmony_ci interrupts = <0 90 1>; 628c2ecf20Sopenharmony_ci clocks = <&clkc_AO CLKID_AO_UART1>; 638c2ecf20Sopenharmony_ci resets = <&clkc_AO RESET_AO_UART1>; 648c2ecf20Sopenharmony_ci }; 65