18c2ecf20Sopenharmony_ciDevice State Configuration Registers 28c2ecf20Sopenharmony_ci------------------------------------ 38c2ecf20Sopenharmony_ci 48c2ecf20Sopenharmony_ciTI C6X SoCs contain a region of miscellaneous registers which provide various 58c2ecf20Sopenharmony_cifunction for SoC control or status. Details vary considerably among from SoC 68c2ecf20Sopenharmony_cito SoC with no two being alike. 78c2ecf20Sopenharmony_ci 88c2ecf20Sopenharmony_ciIn general, the Device State Configuration Registers (DSCR) will provide one or 98c2ecf20Sopenharmony_cimore configuration registers often protected by a lock register where one or 108c2ecf20Sopenharmony_cimore key values must be written to a lock register in order to unlock the 118c2ecf20Sopenharmony_ciconfiguration register for writes. These configuration register may be used to 128c2ecf20Sopenharmony_cienable (and disable in some cases) SoC pin drivers, select peripheral clock 138c2ecf20Sopenharmony_cisources (internal or pin), etc. In some cases, a configuration register is 148c2ecf20Sopenharmony_ciwrite once or the individual bits are write once. In addition to device config, 158c2ecf20Sopenharmony_cithe DSCR block may provide registers which are used to reset peripherals, 168c2ecf20Sopenharmony_ciprovide device ID information, provide ethernet MAC addresses, as well as other 178c2ecf20Sopenharmony_cimiscellaneous functions. 188c2ecf20Sopenharmony_ci 198c2ecf20Sopenharmony_ciFor device state control (enable/disable), each device control is assigned an 208c2ecf20Sopenharmony_ciid which is used by individual device drivers to control the state as needed. 218c2ecf20Sopenharmony_ci 228c2ecf20Sopenharmony_ciRequired properties: 238c2ecf20Sopenharmony_ci 248c2ecf20Sopenharmony_ci- compatible: must be "ti,c64x+dscr" 258c2ecf20Sopenharmony_ci- reg: register area base and size 268c2ecf20Sopenharmony_ci 278c2ecf20Sopenharmony_ciOptional properties: 288c2ecf20Sopenharmony_ci 298c2ecf20Sopenharmony_ci NOTE: These are optional in that not all SoCs will have all properties. For 308c2ecf20Sopenharmony_ci SoCs which do support a given property, leaving the property out of the 318c2ecf20Sopenharmony_ci device tree will result in reduced functionality or possibly driver 328c2ecf20Sopenharmony_ci failure. 338c2ecf20Sopenharmony_ci 348c2ecf20Sopenharmony_ci- ti,dscr-devstat 358c2ecf20Sopenharmony_ci offset of the devstat register 368c2ecf20Sopenharmony_ci 378c2ecf20Sopenharmony_ci- ti,dscr-silicon-rev 388c2ecf20Sopenharmony_ci offset, start bit, and bitsize of silicon revision field 398c2ecf20Sopenharmony_ci 408c2ecf20Sopenharmony_ci- ti,dscr-rmii-resets 418c2ecf20Sopenharmony_ci offset and bitmask of RMII reset field. May have multiple tuples if more 428c2ecf20Sopenharmony_ci than one ethernet port is available. 438c2ecf20Sopenharmony_ci 448c2ecf20Sopenharmony_ci- ti,dscr-locked-regs 458c2ecf20Sopenharmony_ci possibly multiple tuples describing registers which are write protected by 468c2ecf20Sopenharmony_ci a lock register. Each tuple consists of the register offset, lock register 478c2ecf20Sopenharmony_ci offsset, and the key value used to unlock the register. 488c2ecf20Sopenharmony_ci 498c2ecf20Sopenharmony_ci- ti,dscr-kick-regs 508c2ecf20Sopenharmony_ci offset and key values of two "kick" registers used to write protect other 518c2ecf20Sopenharmony_ci registers in DSCR. On SoCs using kick registers, the first key must be 528c2ecf20Sopenharmony_ci written to the first kick register and the second key must be written to 538c2ecf20Sopenharmony_ci the second register before other registers in the area are write-enabled. 548c2ecf20Sopenharmony_ci 558c2ecf20Sopenharmony_ci- ti,dscr-mac-fuse-regs 568c2ecf20Sopenharmony_ci MAC addresses are contained in two registers. Each element of a MAC address 578c2ecf20Sopenharmony_ci is contained in a single byte. This property has two tuples. Each tuple has 588c2ecf20Sopenharmony_ci a register offset and four cells representing bytes in the register from 598c2ecf20Sopenharmony_ci most significant to least. The value of these four cells is the MAC byte 608c2ecf20Sopenharmony_ci index (1-6) of the byte within the register. A value of 0 means the byte 618c2ecf20Sopenharmony_ci is unused in the MAC address. 628c2ecf20Sopenharmony_ci 638c2ecf20Sopenharmony_ci- ti,dscr-devstate-ctl-regs 648c2ecf20Sopenharmony_ci This property describes the bitfields used to control the state of devices. 658c2ecf20Sopenharmony_ci Each tuple describes a range of identical bitfields used to control one or 668c2ecf20Sopenharmony_ci more devices (one bitfield per device). The layout of each tuple is: 678c2ecf20Sopenharmony_ci 688c2ecf20Sopenharmony_ci start_id num_ids reg enable disable start_bit nbits 698c2ecf20Sopenharmony_ci 708c2ecf20Sopenharmony_ci Where: 718c2ecf20Sopenharmony_ci start_id is device id for the first device control in the range 728c2ecf20Sopenharmony_ci num_ids is the number of device controls in the range 738c2ecf20Sopenharmony_ci reg is the offset of the register holding the control bits 748c2ecf20Sopenharmony_ci enable is the value to enable a device 758c2ecf20Sopenharmony_ci disable is the value to disable a device (0xffffffff if cannot disable) 768c2ecf20Sopenharmony_ci start_bit is the bit number of the first bit in the range 778c2ecf20Sopenharmony_ci nbits is the number of bits per device control 788c2ecf20Sopenharmony_ci 798c2ecf20Sopenharmony_ci- ti,dscr-devstate-stat-regs 808c2ecf20Sopenharmony_ci This property describes the bitfields used to provide device state status 818c2ecf20Sopenharmony_ci for device states controlled by the DSCR. Each tuple describes a range of 828c2ecf20Sopenharmony_ci identical bitfields used to provide status for one or more devices (one 838c2ecf20Sopenharmony_ci bitfield per device). The layout of each tuple is: 848c2ecf20Sopenharmony_ci 858c2ecf20Sopenharmony_ci start_id num_ids reg enable disable start_bit nbits 868c2ecf20Sopenharmony_ci 878c2ecf20Sopenharmony_ci Where: 888c2ecf20Sopenharmony_ci start_id is device id for the first device status in the range 898c2ecf20Sopenharmony_ci num_ids is the number of devices covered by the range 908c2ecf20Sopenharmony_ci reg is the offset of the register holding the status bits 918c2ecf20Sopenharmony_ci enable is the value indicating device is enabled 928c2ecf20Sopenharmony_ci disable is the value indicating device is disabled 938c2ecf20Sopenharmony_ci start_bit is the bit number of the first bit in the range 948c2ecf20Sopenharmony_ci nbits is the number of bits per device status 958c2ecf20Sopenharmony_ci 968c2ecf20Sopenharmony_ci- ti,dscr-privperm 978c2ecf20Sopenharmony_ci Offset and default value for register used to set access privilege for 988c2ecf20Sopenharmony_ci some SoC devices. 998c2ecf20Sopenharmony_ci 1008c2ecf20Sopenharmony_ci 1018c2ecf20Sopenharmony_ciExample: 1028c2ecf20Sopenharmony_ci 1038c2ecf20Sopenharmony_ci device-state-config-regs@2a80000 { 1048c2ecf20Sopenharmony_ci compatible = "ti,c64x+dscr"; 1058c2ecf20Sopenharmony_ci reg = <0x02a80000 0x41000>; 1068c2ecf20Sopenharmony_ci 1078c2ecf20Sopenharmony_ci ti,dscr-devstat = <0>; 1088c2ecf20Sopenharmony_ci ti,dscr-silicon-rev = <8 28 0xf>; 1098c2ecf20Sopenharmony_ci ti,dscr-rmii-resets = <0x40020 0x00040000>; 1108c2ecf20Sopenharmony_ci 1118c2ecf20Sopenharmony_ci ti,dscr-locked-regs = <0x40008 0x40004 0x0f0a0b00>; 1128c2ecf20Sopenharmony_ci ti,dscr-devstate-ctl-regs = 1138c2ecf20Sopenharmony_ci <0 12 0x40008 1 0 0 2 1148c2ecf20Sopenharmony_ci 12 1 0x40008 3 0 30 2 1158c2ecf20Sopenharmony_ci 13 2 0x4002c 1 0xffffffff 0 1>; 1168c2ecf20Sopenharmony_ci ti,dscr-devstate-stat-regs = 1178c2ecf20Sopenharmony_ci <0 10 0x40014 1 0 0 3 1188c2ecf20Sopenharmony_ci 10 2 0x40018 1 0 0 3>; 1198c2ecf20Sopenharmony_ci 1208c2ecf20Sopenharmony_ci ti,dscr-mac-fuse-regs = <0x700 1 2 3 4 1218c2ecf20Sopenharmony_ci 0x704 5 6 0 0>; 1228c2ecf20Sopenharmony_ci 1238c2ecf20Sopenharmony_ci ti,dscr-privperm = <0x41c 0xaaaaaaaa>; 1248c2ecf20Sopenharmony_ci 1258c2ecf20Sopenharmony_ci ti,dscr-kick-regs = <0x38 0x83E70B13 1268c2ecf20Sopenharmony_ci 0x3c 0x95A4F1E0>; 1278c2ecf20Sopenharmony_ci }; 128