18c2ecf20Sopenharmony_ciC6X PLL Clock Controllers 28c2ecf20Sopenharmony_ci------------------------- 38c2ecf20Sopenharmony_ci 48c2ecf20Sopenharmony_ciThis is a first-cut support for the SoC clock controllers. This is still 58c2ecf20Sopenharmony_ciunder development and will probably change as the common device tree 68c2ecf20Sopenharmony_ciclock support is added to the kernel. 78c2ecf20Sopenharmony_ci 88c2ecf20Sopenharmony_ciRequired properties: 98c2ecf20Sopenharmony_ci 108c2ecf20Sopenharmony_ci- compatible: "ti,c64x+pll" 118c2ecf20Sopenharmony_ci May also have SoC-specific value to support SoC-specific initialization 128c2ecf20Sopenharmony_ci in the driver. One of: 138c2ecf20Sopenharmony_ci "ti,c6455-pll" 148c2ecf20Sopenharmony_ci "ti,c6457-pll" 158c2ecf20Sopenharmony_ci "ti,c6472-pll" 168c2ecf20Sopenharmony_ci "ti,c6474-pll" 178c2ecf20Sopenharmony_ci 188c2ecf20Sopenharmony_ci- reg: base address and size of register area 198c2ecf20Sopenharmony_ci- clock-frequency: input clock frequency in hz 208c2ecf20Sopenharmony_ci 218c2ecf20Sopenharmony_ci 228c2ecf20Sopenharmony_ciOptional properties: 238c2ecf20Sopenharmony_ci 248c2ecf20Sopenharmony_ci- ti,c64x+pll-bypass-delay: CPU cycles to delay when entering bypass mode 258c2ecf20Sopenharmony_ci 268c2ecf20Sopenharmony_ci- ti,c64x+pll-reset-delay: CPU cycles to delay after PLL reset 278c2ecf20Sopenharmony_ci 288c2ecf20Sopenharmony_ci- ti,c64x+pll-lock-delay: CPU cycles to delay after PLL frequency change 298c2ecf20Sopenharmony_ci 308c2ecf20Sopenharmony_ciExample: 318c2ecf20Sopenharmony_ci 328c2ecf20Sopenharmony_ci clock-controller@29a0000 { 338c2ecf20Sopenharmony_ci compatible = "ti,c6472-pll", "ti,c64x+pll"; 348c2ecf20Sopenharmony_ci reg = <0x029a0000 0x200>; 358c2ecf20Sopenharmony_ci clock-frequency = <25000000>; 368c2ecf20Sopenharmony_ci 378c2ecf20Sopenharmony_ci ti,c64x+pll-bypass-delay = <200>; 388c2ecf20Sopenharmony_ci ti,c64x+pll-reset-delay = <12000>; 398c2ecf20Sopenharmony_ci ti,c64x+pll-lock-delay = <80000>; 408c2ecf20Sopenharmony_ci }; 41