18c2ecf20Sopenharmony_ciBroadcom GISB bus Arbiter controller 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciRequired properties: 48c2ecf20Sopenharmony_ci 58c2ecf20Sopenharmony_ci- compatible: 68c2ecf20Sopenharmony_ci "brcm,bcm7278-gisb-arb" for V7 28nm chips 78c2ecf20Sopenharmony_ci "brcm,gisb-arb" or "brcm,bcm7445-gisb-arb" for other 28nm chips 88c2ecf20Sopenharmony_ci "brcm,bcm7435-gisb-arb" for newer 40nm chips 98c2ecf20Sopenharmony_ci "brcm,bcm7400-gisb-arb" for older 40nm chips and all 65nm chips 108c2ecf20Sopenharmony_ci "brcm,bcm7038-gisb-arb" for 130nm chips 118c2ecf20Sopenharmony_ci- reg: specifies the base physical address and size of the registers 128c2ecf20Sopenharmony_ci- interrupts: specifies the two interrupts (timeout and TEA) to be used from 138c2ecf20Sopenharmony_ci the parent interrupt controller. A third optional interrupt may be specified 148c2ecf20Sopenharmony_ci for breakpoints. 158c2ecf20Sopenharmony_ci 168c2ecf20Sopenharmony_ciOptional properties: 178c2ecf20Sopenharmony_ci 188c2ecf20Sopenharmony_ci- brcm,gisb-arb-master-mask: 32-bits wide bitmask used to specify which GISB 198c2ecf20Sopenharmony_ci masters are valid at the system level 208c2ecf20Sopenharmony_ci- brcm,gisb-arb-master-names: string list of the litteral name of the GISB 218c2ecf20Sopenharmony_ci masters. Should match the number of bits set in brcm,gisb-master-mask and 228c2ecf20Sopenharmony_ci the order in which they appear 238c2ecf20Sopenharmony_ci 248c2ecf20Sopenharmony_ciExample: 258c2ecf20Sopenharmony_ci 268c2ecf20Sopenharmony_cigisb-arb@f0400000 { 278c2ecf20Sopenharmony_ci compatible = "brcm,gisb-arb"; 288c2ecf20Sopenharmony_ci reg = <0xf0400000 0x800>; 298c2ecf20Sopenharmony_ci interrupts = <0>, <2>; 308c2ecf20Sopenharmony_ci interrupt-parent = <&sun_l2_intc>; 318c2ecf20Sopenharmony_ci 328c2ecf20Sopenharmony_ci brcm,gisb-arb-master-mask = <0x7>; 338c2ecf20Sopenharmony_ci brcm,gisb-arb-master-names = "bsp_0", "scpu_0", "cpu_0"; 348c2ecf20Sopenharmony_ci}; 35