18c2ecf20Sopenharmony_ciST-Ericsson Ux500 boards 28c2ecf20Sopenharmony_ci------------------------ 38c2ecf20Sopenharmony_ci 48c2ecf20Sopenharmony_ciRequired properties (in root node) one of these: 58c2ecf20Sopenharmony_ci compatible = "st-ericsson,mop500" (legacy) 68c2ecf20Sopenharmony_ci compatible = "st-ericsson,u8500" 78c2ecf20Sopenharmony_ci 88c2ecf20Sopenharmony_ciRequired node (under root node): 98c2ecf20Sopenharmony_ci 108c2ecf20Sopenharmony_cisoc: represents the system-on-chip and contains the chip 118c2ecf20Sopenharmony_ciperipherals 128c2ecf20Sopenharmony_ci 138c2ecf20Sopenharmony_ciRequired property of soc node, one of these: 148c2ecf20Sopenharmony_ci compatible = "stericsson,db8500" 158c2ecf20Sopenharmony_ci 168c2ecf20Sopenharmony_ciRequired subnodes under soc node: 178c2ecf20Sopenharmony_ci 188c2ecf20Sopenharmony_cibackupram: (used for CPU spin tables and for storing data 198c2ecf20Sopenharmony_ciduring retention, system won't boot without this): 208c2ecf20Sopenharmony_ci compatible = "ste,dbx500-backupram" 218c2ecf20Sopenharmony_ci 228c2ecf20Sopenharmony_ciscu: 238c2ecf20Sopenharmony_ci see binding for arm/scu.txt 248c2ecf20Sopenharmony_ci 258c2ecf20Sopenharmony_ciinterrupt-controller: 268c2ecf20Sopenharmony_ci see binding for interrupt-controller/arm,gic.txt 278c2ecf20Sopenharmony_ci 288c2ecf20Sopenharmony_citimer: 298c2ecf20Sopenharmony_ci see binding for timer/arm,twd.txt 308c2ecf20Sopenharmony_ci 318c2ecf20Sopenharmony_ciclocks: 328c2ecf20Sopenharmony_ci see binding for clocks/ux500.txt 338c2ecf20Sopenharmony_ci 348c2ecf20Sopenharmony_ciExample: 358c2ecf20Sopenharmony_ci 368c2ecf20Sopenharmony_ci/dts-v1/; 378c2ecf20Sopenharmony_ci 388c2ecf20Sopenharmony_ci/ { 398c2ecf20Sopenharmony_ci model = "ST-Ericsson HREF (pre-v60) and ST UIB"; 408c2ecf20Sopenharmony_ci compatible = "st-ericsson,mop500", "st-ericsson,u8500"; 418c2ecf20Sopenharmony_ci 428c2ecf20Sopenharmony_ci soc { 438c2ecf20Sopenharmony_ci #address-cells = <1>; 448c2ecf20Sopenharmony_ci #size-cells = <1>; 458c2ecf20Sopenharmony_ci compatible = "stericsson,db8500"; 468c2ecf20Sopenharmony_ci interrupt-parent = <&intc>; 478c2ecf20Sopenharmony_ci ranges; 488c2ecf20Sopenharmony_ci 498c2ecf20Sopenharmony_ci backupram@80150000 { 508c2ecf20Sopenharmony_ci compatible = "ste,dbx500-backupram"; 518c2ecf20Sopenharmony_ci reg = <0x80150000 0x2000>; 528c2ecf20Sopenharmony_ci }; 538c2ecf20Sopenharmony_ci 548c2ecf20Sopenharmony_ci intc: interrupt-controller@a0411000 { 558c2ecf20Sopenharmony_ci compatible = "arm,cortex-a9-gic"; 568c2ecf20Sopenharmony_ci #interrupt-cells = <3>; 578c2ecf20Sopenharmony_ci #address-cells = <1>; 588c2ecf20Sopenharmony_ci interrupt-controller; 598c2ecf20Sopenharmony_ci reg = <0xa0411000 0x1000>, 608c2ecf20Sopenharmony_ci <0xa0410100 0x100>; 618c2ecf20Sopenharmony_ci }; 628c2ecf20Sopenharmony_ci 638c2ecf20Sopenharmony_ci scu@a0410000 { 648c2ecf20Sopenharmony_ci compatible = "arm,cortex-a9-scu"; 658c2ecf20Sopenharmony_ci reg = <0xa0410000 0x100>; 668c2ecf20Sopenharmony_ci }; 678c2ecf20Sopenharmony_ci 688c2ecf20Sopenharmony_ci timer@a0410600 { 698c2ecf20Sopenharmony_ci compatible = "arm,cortex-a9-twd-timer"; 708c2ecf20Sopenharmony_ci reg = <0xa0410600 0x20>; 718c2ecf20Sopenharmony_ci interrupts = <1 13 0x304>; /* IRQ level high per-CPU */ 728c2ecf20Sopenharmony_ci clocks = <&smp_twd_clk>; 738c2ecf20Sopenharmony_ci }; 748c2ecf20Sopenharmony_ci 758c2ecf20Sopenharmony_ci clocks { 768c2ecf20Sopenharmony_ci compatible = "stericsson,u8500-clks"; 778c2ecf20Sopenharmony_ci 788c2ecf20Sopenharmony_ci smp_twd_clk: smp-twd-clock { 798c2ecf20Sopenharmony_ci #clock-cells = <0>; 808c2ecf20Sopenharmony_ci }; 818c2ecf20Sopenharmony_ci }; 828c2ecf20Sopenharmony_ci }; 838c2ecf20Sopenharmony_ci}; 84