18c2ecf20Sopenharmony_ciMediatek vdecsys controller
28c2ecf20Sopenharmony_ci============================
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48c2ecf20Sopenharmony_ciThe Mediatek vdecsys controller provides various clocks to the system.
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68c2ecf20Sopenharmony_ciRequired Properties:
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88c2ecf20Sopenharmony_ci- compatible: Should be one of:
98c2ecf20Sopenharmony_ci	- "mediatek,mt2701-vdecsys", "syscon"
108c2ecf20Sopenharmony_ci	- "mediatek,mt2712-vdecsys", "syscon"
118c2ecf20Sopenharmony_ci	- "mediatek,mt6779-vdecsys", "syscon"
128c2ecf20Sopenharmony_ci	- "mediatek,mt6797-vdecsys", "syscon"
138c2ecf20Sopenharmony_ci	- "mediatek,mt7623-vdecsys", "mediatek,mt2701-vdecsys", "syscon"
148c2ecf20Sopenharmony_ci	- "mediatek,mt8167-vdecsys", "syscon"
158c2ecf20Sopenharmony_ci	- "mediatek,mt8173-vdecsys", "syscon"
168c2ecf20Sopenharmony_ci	- "mediatek,mt8183-vdecsys", "syscon"
178c2ecf20Sopenharmony_ci- #clock-cells: Must be 1
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198c2ecf20Sopenharmony_ciThe vdecsys controller uses the common clk binding from
208c2ecf20Sopenharmony_ciDocumentation/devicetree/bindings/clock/clock-bindings.txt
218c2ecf20Sopenharmony_ciThe available clocks are defined in dt-bindings/clock/mt*-clk.h.
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238c2ecf20Sopenharmony_ciExample:
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258c2ecf20Sopenharmony_civdecsys: clock-controller@16000000 {
268c2ecf20Sopenharmony_ci	compatible = "mediatek,mt8173-vdecsys", "syscon";
278c2ecf20Sopenharmony_ci	reg = <0 0x16000000 0 0x1000>;
288c2ecf20Sopenharmony_ci	#clock-cells = <1>;
298c2ecf20Sopenharmony_ci};
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