18c2ecf20Sopenharmony_ciMediaTek SSUSBSYS controller 28c2ecf20Sopenharmony_ci============================ 38c2ecf20Sopenharmony_ci 48c2ecf20Sopenharmony_ciThe MediaTek SSUSBSYS controller provides various clocks to the system. 58c2ecf20Sopenharmony_ci 68c2ecf20Sopenharmony_ciRequired Properties: 78c2ecf20Sopenharmony_ci 88c2ecf20Sopenharmony_ci- compatible: Should be: 98c2ecf20Sopenharmony_ci - "mediatek,mt7622-ssusbsys", "syscon" 108c2ecf20Sopenharmony_ci - "mediatek,mt7629-ssusbsys", "syscon" 118c2ecf20Sopenharmony_ci- #clock-cells: Must be 1 128c2ecf20Sopenharmony_ci- #reset-cells: Must be 1 138c2ecf20Sopenharmony_ci 148c2ecf20Sopenharmony_ciThe SSUSBSYS controller uses the common clk binding from 158c2ecf20Sopenharmony_ciDocumentation/devicetree/bindings/clock/clock-bindings.txt 168c2ecf20Sopenharmony_ciThe available clocks are defined in dt-bindings/clock/mt*-clk.h. 178c2ecf20Sopenharmony_ci 188c2ecf20Sopenharmony_ciExample: 198c2ecf20Sopenharmony_ci 208c2ecf20Sopenharmony_cissusbsys: ssusbsys@1a000000 { 218c2ecf20Sopenharmony_ci compatible = "mediatek,mt7622-ssusbsys", "syscon"; 228c2ecf20Sopenharmony_ci reg = <0 0x1a000000 0 0x1000>; 238c2ecf20Sopenharmony_ci #clock-cells = <1>; 248c2ecf20Sopenharmony_ci #reset-cells = <1>; 258c2ecf20Sopenharmony_ci}; 26