18c2ecf20Sopenharmony_ciMediatek mipi0a (mipi_rx_ana_csi0a) controller
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48c2ecf20Sopenharmony_ciThe Mediatek mipi0a controller provides various clocks
58c2ecf20Sopenharmony_cito the system.
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78c2ecf20Sopenharmony_ciRequired Properties:
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98c2ecf20Sopenharmony_ci- compatible: Should be one of:
108c2ecf20Sopenharmony_ci	- "mediatek,mt6765-mipi0a", "syscon"
118c2ecf20Sopenharmony_ci- #clock-cells: Must be 1
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138c2ecf20Sopenharmony_ciThe mipi0a controller uses the common clk binding from
148c2ecf20Sopenharmony_ciDocumentation/devicetree/bindings/clock/clock-bindings.txt
158c2ecf20Sopenharmony_ciThe available clocks are defined in dt-bindings/clock/mt*-clk.h.
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178c2ecf20Sopenharmony_ciThe mipi0a controller also uses the common power domain from
188c2ecf20Sopenharmony_ciDocumentation/devicetree/bindings/soc/mediatek/scpsys.txt
198c2ecf20Sopenharmony_ciThe available power doamins are defined in dt-bindings/power/mt*-power.h.
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218c2ecf20Sopenharmony_ciExample:
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238c2ecf20Sopenharmony_cimipi0a: clock-controller@11c10000 {
248c2ecf20Sopenharmony_ci	compatible = "mediatek,mt6765-mipi0a", "syscon";
258c2ecf20Sopenharmony_ci	reg = <0 0x11c10000 0 0x1000>;
268c2ecf20Sopenharmony_ci	power-domains = <&scpsys MT6765_POWER_DOMAIN_CAM>;
278c2ecf20Sopenharmony_ci	#clock-cells = <1>;
288c2ecf20Sopenharmony_ci};
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