18c2ecf20Sopenharmony_ciMediatek hifsys controller 28c2ecf20Sopenharmony_ci============================ 38c2ecf20Sopenharmony_ci 48c2ecf20Sopenharmony_ciThe Mediatek hifsys controller provides various clocks and reset 58c2ecf20Sopenharmony_cioutputs to the system. 68c2ecf20Sopenharmony_ci 78c2ecf20Sopenharmony_ciRequired Properties: 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_ci- compatible: Should be: 108c2ecf20Sopenharmony_ci - "mediatek,mt2701-hifsys", "syscon" 118c2ecf20Sopenharmony_ci - "mediatek,mt7622-hifsys", "syscon" 128c2ecf20Sopenharmony_ci - "mediatek,mt7623-hifsys", "mediatek,mt2701-hifsys", "syscon" 138c2ecf20Sopenharmony_ci- #clock-cells: Must be 1 148c2ecf20Sopenharmony_ci 158c2ecf20Sopenharmony_ciThe hifsys controller uses the common clk binding from 168c2ecf20Sopenharmony_ciDocumentation/devicetree/bindings/clock/clock-bindings.txt 178c2ecf20Sopenharmony_ciThe available clocks are defined in dt-bindings/clock/mt*-clk.h. 188c2ecf20Sopenharmony_ci 198c2ecf20Sopenharmony_ciExample: 208c2ecf20Sopenharmony_ci 218c2ecf20Sopenharmony_cihifsys: clock-controller@1a000000 { 228c2ecf20Sopenharmony_ci compatible = "mediatek,mt2701-hifsys", "syscon"; 238c2ecf20Sopenharmony_ci reg = <0 0x1a000000 0 0x1000>; 248c2ecf20Sopenharmony_ci #clock-cells = <1>; 258c2ecf20Sopenharmony_ci #reset-cells = <1>; 268c2ecf20Sopenharmony_ci}; 27