18c2ecf20Sopenharmony_ciMediaTek g3dsys controller
28c2ecf20Sopenharmony_ci============================
38c2ecf20Sopenharmony_ci
48c2ecf20Sopenharmony_ciThe MediaTek g3dsys controller provides various clocks and reset controller to
58c2ecf20Sopenharmony_cithe GPU.
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78c2ecf20Sopenharmony_ciRequired Properties:
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98c2ecf20Sopenharmony_ci- compatible: Should be:
108c2ecf20Sopenharmony_ci	- "mediatek,mt2701-g3dsys", "syscon":
118c2ecf20Sopenharmony_ci		for MT2701 SoC
128c2ecf20Sopenharmony_ci	- "mediatek,mt7623-g3dsys", "mediatek,mt2701-g3dsys", "syscon":
138c2ecf20Sopenharmony_ci		for MT7623 SoC
148c2ecf20Sopenharmony_ci- #clock-cells: Must be 1
158c2ecf20Sopenharmony_ci- #reset-cells: Must be 1
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178c2ecf20Sopenharmony_ciThe g3dsys controller uses the common clk binding from
188c2ecf20Sopenharmony_ciDocumentation/devicetree/bindings/clock/clock-bindings.txt
198c2ecf20Sopenharmony_ciThe available clocks are defined in dt-bindings/clock/mt*-clk.h.
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218c2ecf20Sopenharmony_ciExample:
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238c2ecf20Sopenharmony_cig3dsys: clock-controller@13000000 {
248c2ecf20Sopenharmony_ci	compatible = "mediatek,mt7623-g3dsys",
258c2ecf20Sopenharmony_ci		     "mediatek,mt2701-g3dsys",
268c2ecf20Sopenharmony_ci		     "syscon";
278c2ecf20Sopenharmony_ci	reg = <0 0x13000000 0 0x200>;
288c2ecf20Sopenharmony_ci	#clock-cells = <1>;
298c2ecf20Sopenharmony_ci	#reset-cells = <1>;
308c2ecf20Sopenharmony_ci};
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