18c2ecf20Sopenharmony_ciMediatek ethsys controller
28c2ecf20Sopenharmony_ci============================
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48c2ecf20Sopenharmony_ciThe Mediatek ethsys controller provides various clocks to the system.
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68c2ecf20Sopenharmony_ciRequired Properties:
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88c2ecf20Sopenharmony_ci- compatible: Should be:
98c2ecf20Sopenharmony_ci	- "mediatek,mt2701-ethsys", "syscon"
108c2ecf20Sopenharmony_ci	- "mediatek,mt7622-ethsys", "syscon"
118c2ecf20Sopenharmony_ci	- "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon"
128c2ecf20Sopenharmony_ci	- "mediatek,mt7629-ethsys", "syscon"
138c2ecf20Sopenharmony_ci- #clock-cells: Must be 1
148c2ecf20Sopenharmony_ci- #reset-cells: Must be 1
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168c2ecf20Sopenharmony_ciThe ethsys controller uses the common clk binding from
178c2ecf20Sopenharmony_ciDocumentation/devicetree/bindings/clock/clock-bindings.txt
188c2ecf20Sopenharmony_ciThe available clocks are defined in dt-bindings/clock/mt*-clk.h.
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208c2ecf20Sopenharmony_ciExample:
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228c2ecf20Sopenharmony_ciethsys: clock-controller@1b000000 {
238c2ecf20Sopenharmony_ci	compatible = "mediatek,mt2701-ethsys", "syscon";
248c2ecf20Sopenharmony_ci	reg = <0 0x1b000000 0 0x1000>;
258c2ecf20Sopenharmony_ci	#clock-cells = <1>;
268c2ecf20Sopenharmony_ci	#reset-cells = <1>;
278c2ecf20Sopenharmony_ci};
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