18c2ecf20Sopenharmony_ciCortina systems Gemini platforms 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciThe Gemini SoC is the project name for an ARMv4 FA525-based SoC originally 48c2ecf20Sopenharmony_ciproduced by Storlink Semiconductor around 2005. The company was renamed 58c2ecf20Sopenharmony_cilater renamed Storm Semiconductor. The chip product name is Storlink SL3516. 68c2ecf20Sopenharmony_ciIt was derived from earlier products from Storm named SL3316 (Centroid) and 78c2ecf20Sopenharmony_ciSL3512 (Bulverde). 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_ciStorm Semiconductor was acquired by Cortina Systems in 2008 and the SoC was 108c2ecf20Sopenharmony_ciproduced and used for NAS and similar usecases. In 2014 Cortina Systems was 118c2ecf20Sopenharmony_ciin turn acquired by Inphi, who seem to have discontinued this product family. 128c2ecf20Sopenharmony_ci 138c2ecf20Sopenharmony_ciMany of the IP blocks used in the SoC comes from Faraday Technology. 148c2ecf20Sopenharmony_ci 158c2ecf20Sopenharmony_ciRequired properties (in root node): 168c2ecf20Sopenharmony_ci compatible = "cortina,gemini"; 178c2ecf20Sopenharmony_ci 188c2ecf20Sopenharmony_ciRequired nodes: 198c2ecf20Sopenharmony_ci 208c2ecf20Sopenharmony_ci- soc: the SoC should be represented by a simple bus encompassing all the 218c2ecf20Sopenharmony_ci onchip devices, this is referred to as the soc bus node. 228c2ecf20Sopenharmony_ci 238c2ecf20Sopenharmony_ci- syscon: the soc bus node must have a system controller node pointing to the 248c2ecf20Sopenharmony_ci global control registers, with the compatible string 258c2ecf20Sopenharmony_ci "cortina,gemini-syscon", "syscon"; 268c2ecf20Sopenharmony_ci 278c2ecf20Sopenharmony_ci Required properties on the syscon: 288c2ecf20Sopenharmony_ci - reg: syscon register location and size. 298c2ecf20Sopenharmony_ci - #clock-cells: should be set to <1> - the system controller is also a 308c2ecf20Sopenharmony_ci clock provider. 318c2ecf20Sopenharmony_ci - #reset-cells: should be set to <1> - the system controller is also a 328c2ecf20Sopenharmony_ci reset line provider. 338c2ecf20Sopenharmony_ci 348c2ecf20Sopenharmony_ci The clock sources have shorthand defines in the include file: 358c2ecf20Sopenharmony_ci <dt-bindings/clock/cortina,gemini-clock.h> 368c2ecf20Sopenharmony_ci 378c2ecf20Sopenharmony_ci The reset lines have shorthand defines in the include file: 388c2ecf20Sopenharmony_ci <dt-bindings/reset/cortina,gemini-reset.h> 398c2ecf20Sopenharmony_ci 408c2ecf20Sopenharmony_ci- timer: the soc bus node must have a timer node pointing to the SoC timer 418c2ecf20Sopenharmony_ci block, with the compatible string "cortina,gemini-timer" 428c2ecf20Sopenharmony_ci See: clocksource/cortina,gemini-timer.txt 438c2ecf20Sopenharmony_ci 448c2ecf20Sopenharmony_ci- interrupt-controller: the sob bus node must have an interrupt controller 458c2ecf20Sopenharmony_ci node pointing to the SoC interrupt controller block, with the compatible 468c2ecf20Sopenharmony_ci string "cortina,gemini-interrupt-controller" 478c2ecf20Sopenharmony_ci See interrupt-controller/cortina,gemini-interrupt-controller.txt 488c2ecf20Sopenharmony_ci 498c2ecf20Sopenharmony_ciExample: 508c2ecf20Sopenharmony_ci 518c2ecf20Sopenharmony_ci/ { 528c2ecf20Sopenharmony_ci model = "Foo Gemini Machine"; 538c2ecf20Sopenharmony_ci compatible = "cortina,gemini"; 548c2ecf20Sopenharmony_ci #address-cells = <1>; 558c2ecf20Sopenharmony_ci #size-cells = <1>; 568c2ecf20Sopenharmony_ci 578c2ecf20Sopenharmony_ci memory { 588c2ecf20Sopenharmony_ci device_type = "memory"; 598c2ecf20Sopenharmony_ci reg = <0x00000000 0x8000000>; 608c2ecf20Sopenharmony_ci }; 618c2ecf20Sopenharmony_ci 628c2ecf20Sopenharmony_ci soc { 638c2ecf20Sopenharmony_ci #address-cells = <1>; 648c2ecf20Sopenharmony_ci #size-cells = <1>; 658c2ecf20Sopenharmony_ci ranges; 668c2ecf20Sopenharmony_ci compatible = "simple-bus"; 678c2ecf20Sopenharmony_ci interrupt-parent = <&intcon>; 688c2ecf20Sopenharmony_ci 698c2ecf20Sopenharmony_ci syscon: syscon@40000000 { 708c2ecf20Sopenharmony_ci compatible = "cortina,gemini-syscon", "syscon"; 718c2ecf20Sopenharmony_ci reg = <0x40000000 0x1000>; 728c2ecf20Sopenharmony_ci #clock-cells = <1>; 738c2ecf20Sopenharmony_ci #reset-cells = <1>; 748c2ecf20Sopenharmony_ci }; 758c2ecf20Sopenharmony_ci 768c2ecf20Sopenharmony_ci uart0: serial@42000000 { 778c2ecf20Sopenharmony_ci compatible = "ns16550a"; 788c2ecf20Sopenharmony_ci reg = <0x42000000 0x100>; 798c2ecf20Sopenharmony_ci resets = <&syscon GEMINI_RESET_UART>; 808c2ecf20Sopenharmony_ci clocks = <&syscon GEMINI_CLK_UART>; 818c2ecf20Sopenharmony_ci interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; 828c2ecf20Sopenharmony_ci reg-shift = <2>; 838c2ecf20Sopenharmony_ci }; 848c2ecf20Sopenharmony_ci 858c2ecf20Sopenharmony_ci timer@43000000 { 868c2ecf20Sopenharmony_ci compatible = "cortina,gemini-timer"; 878c2ecf20Sopenharmony_ci reg = <0x43000000 0x1000>; 888c2ecf20Sopenharmony_ci interrupt-parent = <&intcon>; 898c2ecf20Sopenharmony_ci interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */ 908c2ecf20Sopenharmony_ci <15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */ 918c2ecf20Sopenharmony_ci <16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */ 928c2ecf20Sopenharmony_ci resets = <&syscon GEMINI_RESET_TIMER>; 938c2ecf20Sopenharmony_ci /* APB clock or RTC clock */ 948c2ecf20Sopenharmony_ci clocks = <&syscon GEMINI_CLK_APB>, 958c2ecf20Sopenharmony_ci <&syscon GEMINI_CLK_RTC>; 968c2ecf20Sopenharmony_ci clock-names = "PCLK", "EXTCLK"; 978c2ecf20Sopenharmony_ci syscon = <&syscon>; 988c2ecf20Sopenharmony_ci }; 998c2ecf20Sopenharmony_ci 1008c2ecf20Sopenharmony_ci intcon: interrupt-controller@48000000 { 1018c2ecf20Sopenharmony_ci compatible = "cortina,gemini-interrupt-controller"; 1028c2ecf20Sopenharmony_ci reg = <0x48000000 0x1000>; 1038c2ecf20Sopenharmony_ci resets = <&syscon GEMINI_RESET_INTCON0>; 1048c2ecf20Sopenharmony_ci interrupt-controller; 1058c2ecf20Sopenharmony_ci #interrupt-cells = <2>; 1068c2ecf20Sopenharmony_ci }; 1078c2ecf20Sopenharmony_ci }; 1088c2ecf20Sopenharmony_ci}; 109