18c2ecf20Sopenharmony_ciFreescale Vybrid Miscellaneous System Control - Interrupt Router 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciThe MSCM IP contains multiple sub modules, this binding describes the second 48c2ecf20Sopenharmony_ciblock of registers which control the interrupt router. The interrupt router 58c2ecf20Sopenharmony_ciallows to configure the recipient of each peripheral interrupt. Furthermore 68c2ecf20Sopenharmony_ciit controls the directed processor interrupts. The module is available in all 78c2ecf20Sopenharmony_ciVybrid SoC's but is only really useful in dual core configurations (VF6xx 88c2ecf20Sopenharmony_ciwhich comes with a Cortex-A5/Cortex-M4 combination). 98c2ecf20Sopenharmony_ci 108c2ecf20Sopenharmony_ciRequired properties: 118c2ecf20Sopenharmony_ci- compatible: "fsl,vf610-mscm-ir" 128c2ecf20Sopenharmony_ci- reg: the register range of the MSCM Interrupt Router 138c2ecf20Sopenharmony_ci- fsl,cpucfg: The handle to the MSCM CPU configuration node, required 148c2ecf20Sopenharmony_ci to get the current CPU ID 158c2ecf20Sopenharmony_ci- interrupt-controller: Identifies the node as an interrupt controller 168c2ecf20Sopenharmony_ci- #interrupt-cells: Two cells, interrupt number and cells. 178c2ecf20Sopenharmony_ci The hardware interrupt number according to interrupt 188c2ecf20Sopenharmony_ci assignment of the interrupt router is required. 198c2ecf20Sopenharmony_ci Flags get passed only when using GIC as parent. Flags 208c2ecf20Sopenharmony_ci encoding as documented by the GIC bindings. 218c2ecf20Sopenharmony_ci 228c2ecf20Sopenharmony_ciExample: 238c2ecf20Sopenharmony_ci mscm_ir: interrupt-controller@40001800 { 248c2ecf20Sopenharmony_ci compatible = "fsl,vf610-mscm-ir"; 258c2ecf20Sopenharmony_ci reg = <0x40001800 0x400>; 268c2ecf20Sopenharmony_ci fsl,cpucfg = <&mscm_cpucfg>; 278c2ecf20Sopenharmony_ci interrupt-controller; 288c2ecf20Sopenharmony_ci #interrupt-cells = <2>; 298c2ecf20Sopenharmony_ci interrupt-parent = <&intc>; 308c2ecf20Sopenharmony_ci } 31