18c2ecf20Sopenharmony_ci========================================================= 28c2ecf20Sopenharmony_ciSecondary CPU enable-method "nuvoton,npcm750-smp" binding 38c2ecf20Sopenharmony_ci========================================================= 48c2ecf20Sopenharmony_ci 58c2ecf20Sopenharmony_ciTo apply to all CPUs, a single "nuvoton,npcm750-smp" enable method should be 68c2ecf20Sopenharmony_cidefined in the "cpus" node. 78c2ecf20Sopenharmony_ci 88c2ecf20Sopenharmony_ciEnable method name: "nuvoton,npcm750-smp" 98c2ecf20Sopenharmony_ciCompatible machines: "nuvoton,npcm750" 108c2ecf20Sopenharmony_ciCompatible CPUs: "arm,cortex-a9" 118c2ecf20Sopenharmony_ciRelated properties: (none) 128c2ecf20Sopenharmony_ci 138c2ecf20Sopenharmony_ciNote: 148c2ecf20Sopenharmony_ciThis enable method needs valid nodes compatible with "arm,cortex-a9-scu" and 158c2ecf20Sopenharmony_ci"nuvoton,npcm750-gcr". 168c2ecf20Sopenharmony_ci 178c2ecf20Sopenharmony_ciExample: 188c2ecf20Sopenharmony_ci 198c2ecf20Sopenharmony_ci cpus { 208c2ecf20Sopenharmony_ci #address-cells = <1>; 218c2ecf20Sopenharmony_ci #size-cells = <0>; 228c2ecf20Sopenharmony_ci enable-method = "nuvoton,npcm750-smp"; 238c2ecf20Sopenharmony_ci 248c2ecf20Sopenharmony_ci cpu@0 { 258c2ecf20Sopenharmony_ci device_type = "cpu"; 268c2ecf20Sopenharmony_ci compatible = "arm,cortex-a9"; 278c2ecf20Sopenharmony_ci clocks = <&clk NPCM7XX_CLK_CPU>; 288c2ecf20Sopenharmony_ci clock-names = "clk_cpu"; 298c2ecf20Sopenharmony_ci reg = <0>; 308c2ecf20Sopenharmony_ci next-level-cache = <&L2>; 318c2ecf20Sopenharmony_ci }; 328c2ecf20Sopenharmony_ci 338c2ecf20Sopenharmony_ci cpu@1 { 348c2ecf20Sopenharmony_ci device_type = "cpu"; 358c2ecf20Sopenharmony_ci compatible = "arm,cortex-a9"; 368c2ecf20Sopenharmony_ci clocks = <&clk NPCM7XX_CLK_CPU>; 378c2ecf20Sopenharmony_ci clock-names = "clk_cpu"; 388c2ecf20Sopenharmony_ci reg = <1>; 398c2ecf20Sopenharmony_ci next-level-cache = <&L2>; 408c2ecf20Sopenharmony_ci }; 418c2ecf20Sopenharmony_ci }; 428c2ecf20Sopenharmony_ci 43