18c2ecf20Sopenharmony_ci======================================================== 28c2ecf20Sopenharmony_ciSecondary CPU enable-method "marvell,berlin-smp" binding 38c2ecf20Sopenharmony_ci======================================================== 48c2ecf20Sopenharmony_ci 58c2ecf20Sopenharmony_ciThis document describes the "marvell,berlin-smp" method for enabling secondary 68c2ecf20Sopenharmony_ciCPUs. To apply to all CPUs, a single "marvell,berlin-smp" enable method should 78c2ecf20Sopenharmony_cibe defined in the "cpus" node. 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_ciEnable method name: "marvell,berlin-smp" 108c2ecf20Sopenharmony_ciCompatible machines: "marvell,berlin2" and "marvell,berlin2q" 118c2ecf20Sopenharmony_ciCompatible CPUs: "marvell,pj4b" and "arm,cortex-a9" 128c2ecf20Sopenharmony_ciRelated properties: (none) 138c2ecf20Sopenharmony_ci 148c2ecf20Sopenharmony_ciNote: 158c2ecf20Sopenharmony_ciThis enable method needs valid nodes compatible with "arm,cortex-a9-scu" and 168c2ecf20Sopenharmony_ci"marvell,berlin-cpu-ctrl"[1]. 178c2ecf20Sopenharmony_ci 188c2ecf20Sopenharmony_ciExample: 198c2ecf20Sopenharmony_ci 208c2ecf20Sopenharmony_ci cpus { 218c2ecf20Sopenharmony_ci #address-cells = <1>; 228c2ecf20Sopenharmony_ci #size-cells = <0>; 238c2ecf20Sopenharmony_ci enable-method = "marvell,berlin-smp"; 248c2ecf20Sopenharmony_ci 258c2ecf20Sopenharmony_ci cpu@0 { 268c2ecf20Sopenharmony_ci compatible = "marvell,pj4b"; 278c2ecf20Sopenharmony_ci device_type = "cpu"; 288c2ecf20Sopenharmony_ci next-level-cache = <&l2>; 298c2ecf20Sopenharmony_ci reg = <0>; 308c2ecf20Sopenharmony_ci }; 318c2ecf20Sopenharmony_ci 328c2ecf20Sopenharmony_ci cpu@1 { 338c2ecf20Sopenharmony_ci compatible = "marvell,pj4b"; 348c2ecf20Sopenharmony_ci device_type = "cpu"; 358c2ecf20Sopenharmony_ci next-level-cache = <&l2>; 368c2ecf20Sopenharmony_ci reg = <1>; 378c2ecf20Sopenharmony_ci }; 388c2ecf20Sopenharmony_ci }; 398c2ecf20Sopenharmony_ci 408c2ecf20Sopenharmony_ci-- 418c2ecf20Sopenharmony_ci[1] arm/marvell,berlin.txt 42