18c2ecf20Sopenharmony_ci* ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU) 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores 48c2ecf20Sopenharmony_ciwith a shared L3 memory system, control logic and external interfaces to 58c2ecf20Sopenharmony_ciform a multicore cluster. The PMU enables to gather various statistics on 68c2ecf20Sopenharmony_cithe operations of the DSU. The PMU provides independent 32bit counters that 78c2ecf20Sopenharmony_cican count any of the supported events, along with a 64bit cycle counter. 88c2ecf20Sopenharmony_ciThe PMU is accessed via CPU system registers and has no MMIO component. 98c2ecf20Sopenharmony_ci 108c2ecf20Sopenharmony_ci** DSU PMU required properties: 118c2ecf20Sopenharmony_ci 128c2ecf20Sopenharmony_ci- compatible : should be one of : 138c2ecf20Sopenharmony_ci 148c2ecf20Sopenharmony_ci "arm,dsu-pmu" 158c2ecf20Sopenharmony_ci 168c2ecf20Sopenharmony_ci- interrupts : Exactly 1 SPI must be listed. 178c2ecf20Sopenharmony_ci 188c2ecf20Sopenharmony_ci- cpus : List of phandles for the CPUs connected to this DSU instance. 198c2ecf20Sopenharmony_ci 208c2ecf20Sopenharmony_ci 218c2ecf20Sopenharmony_ci** Example: 228c2ecf20Sopenharmony_ci 238c2ecf20Sopenharmony_cidsu-pmu-0 { 248c2ecf20Sopenharmony_ci compatible = "arm,dsu-pmu"; 258c2ecf20Sopenharmony_ci interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>; 268c2ecf20Sopenharmony_ci cpus = <&cpu_0>, <&cpu_1>; 278c2ecf20Sopenharmony_ci}; 28