18c2ecf20Sopenharmony_ciWhat: /sys/devices/*/<our-device>/fuse 28c2ecf20Sopenharmony_ciDate: February 2014 38c2ecf20Sopenharmony_ciContact: Peter De Schrijver <pdeschrijver@nvidia.com> 48c2ecf20Sopenharmony_ciDescription: read-only access to the efuses on Tegra20, Tegra30, Tegra114 58c2ecf20Sopenharmony_ci and Tegra124 SoC's from NVIDIA. The efuses contain write once 68c2ecf20Sopenharmony_ci data programmed at the factory. The data is layed out in 32bit 78c2ecf20Sopenharmony_ci words in LSB first format. Each bit represents a single value 88c2ecf20Sopenharmony_ci as decoded from the fuse registers. Bits order/assignment 98c2ecf20Sopenharmony_ci exactly matches the HW registers, including any unused bits. 108c2ecf20Sopenharmony_ciUsers: any user space application which wants to read the efuses on 118c2ecf20Sopenharmony_ci Tegra SoC's 12