18c2ecf20Sopenharmony_ciWhat: /sys/bus/i2c/devices/.../bd9571mwv-regulator.*.auto/backup_mode 28c2ecf20Sopenharmony_ciDate: Jul 2018 38c2ecf20Sopenharmony_ciKernelVersion: 4.19 48c2ecf20Sopenharmony_ciContact: Geert Uytterhoeven <geert+renesas@glider.be> 58c2ecf20Sopenharmony_ciDescription: Read/write the current state of DDR Backup Mode, which controls 68c2ecf20Sopenharmony_ci if DDR power rails will be kept powered during system suspend. 78c2ecf20Sopenharmony_ci ("on"/"1" = enabled, "off"/"0" = disabled). 88c2ecf20Sopenharmony_ci Two types of power switches (or control signals) can be used: 98c2ecf20Sopenharmony_ci 108c2ecf20Sopenharmony_ci A. With a momentary power switch (or pulse signal), DDR 118c2ecf20Sopenharmony_ci Backup Mode is enabled by default when available, as the 128c2ecf20Sopenharmony_ci PMIC will be configured only during system suspend. 138c2ecf20Sopenharmony_ci B. With a toggle power switch (or level signal), the 148c2ecf20Sopenharmony_ci following steps must be followed exactly: 158c2ecf20Sopenharmony_ci 168c2ecf20Sopenharmony_ci 1. Configure PMIC for backup mode, to change the role of 178c2ecf20Sopenharmony_ci the accessory power switch from a power switch to a 188c2ecf20Sopenharmony_ci wake-up switch, 198c2ecf20Sopenharmony_ci 2. Switch accessory power switch off, to prepare for 208c2ecf20Sopenharmony_ci system suspend, which is a manual step not controlled 218c2ecf20Sopenharmony_ci by software, 228c2ecf20Sopenharmony_ci 3. Suspend system, 238c2ecf20Sopenharmony_ci 4. Switch accessory power switch on, to resume the 248c2ecf20Sopenharmony_ci system. 258c2ecf20Sopenharmony_ci 268c2ecf20Sopenharmony_ci DDR Backup Mode must be explicitly enabled by the user, 278c2ecf20Sopenharmony_ci to invoke step 1. 288c2ecf20Sopenharmony_ci 298c2ecf20Sopenharmony_ci See also Documentation/devicetree/bindings/mfd/bd9571mwv.txt. 308c2ecf20Sopenharmony_ciUsers: User space applications for embedded boards equipped with a 318c2ecf20Sopenharmony_ci BD9571MWV PMIC. 32