18c2ecf20Sopenharmony_ciWhat: /sys/bus/coresight/devices/<memory_map>.stm/enable_source 28c2ecf20Sopenharmony_ciDate: April 2016 38c2ecf20Sopenharmony_ciKernelVersion: 4.7 48c2ecf20Sopenharmony_ciContact: Mathieu Poirier <mathieu.poirier@linaro.org> 58c2ecf20Sopenharmony_ciDescription: (RW) Enable/disable tracing on this specific trace macrocell. 68c2ecf20Sopenharmony_ci Enabling the trace macrocell implies it has been configured 78c2ecf20Sopenharmony_ci properly and a sink has been identified for it. The path 88c2ecf20Sopenharmony_ci of coresight components linking the source to the sink is 98c2ecf20Sopenharmony_ci configured and managed automatically by the coresight framework. 108c2ecf20Sopenharmony_ci 118c2ecf20Sopenharmony_ciWhat: /sys/bus/coresight/devices/<memory_map>.stm/hwevent_enable 128c2ecf20Sopenharmony_ciDate: April 2016 138c2ecf20Sopenharmony_ciKernelVersion: 4.7 148c2ecf20Sopenharmony_ciContact: Mathieu Poirier <mathieu.poirier@linaro.org> 158c2ecf20Sopenharmony_ciDescription: (RW) Provides access to the HW event enable register, used in 168c2ecf20Sopenharmony_ci conjunction with HW event bank select register. 178c2ecf20Sopenharmony_ci 188c2ecf20Sopenharmony_ciWhat: /sys/bus/coresight/devices/<memory_map>.stm/hwevent_select 198c2ecf20Sopenharmony_ciDate: April 2016 208c2ecf20Sopenharmony_ciKernelVersion: 4.7 218c2ecf20Sopenharmony_ciContact: Mathieu Poirier <mathieu.poirier@linaro.org> 228c2ecf20Sopenharmony_ciDescription: (RW) Gives access to the HW event block select register 238c2ecf20Sopenharmony_ci (STMHEBSR) in order to configure up to 256 channels. Used in 248c2ecf20Sopenharmony_ci conjunction with "hwevent_enable" register as described above. 258c2ecf20Sopenharmony_ci 268c2ecf20Sopenharmony_ciWhat: /sys/bus/coresight/devices/<memory_map>.stm/port_enable 278c2ecf20Sopenharmony_ciDate: April 2016 288c2ecf20Sopenharmony_ciKernelVersion: 4.7 298c2ecf20Sopenharmony_ciContact: Mathieu Poirier <mathieu.poirier@linaro.org> 308c2ecf20Sopenharmony_ciDescription: (RW) Provides access to the stimulus port enable register 318c2ecf20Sopenharmony_ci (STMSPER). Used in conjunction with "port_select" described 328c2ecf20Sopenharmony_ci below. 338c2ecf20Sopenharmony_ci 348c2ecf20Sopenharmony_ciWhat: /sys/bus/coresight/devices/<memory_map>.stm/port_select 358c2ecf20Sopenharmony_ciDate: April 2016 368c2ecf20Sopenharmony_ciKernelVersion: 4.7 378c2ecf20Sopenharmony_ciContact: Mathieu Poirier <mathieu.poirier@linaro.org> 388c2ecf20Sopenharmony_ciDescription: (RW) Used to determine which bank of stimulus port bit in 398c2ecf20Sopenharmony_ci register STMSPER (see above) apply to. 408c2ecf20Sopenharmony_ci 418c2ecf20Sopenharmony_ciWhat: /sys/bus/coresight/devices/<memory_map>.stm/status 428c2ecf20Sopenharmony_ciDate: April 2016 438c2ecf20Sopenharmony_ciKernelVersion: 4.7 448c2ecf20Sopenharmony_ciContact: Mathieu Poirier <mathieu.poirier@linaro.org> 458c2ecf20Sopenharmony_ciDescription: (Read) List various control and status registers. The specific 468c2ecf20Sopenharmony_ci layout and content is driver specific. 478c2ecf20Sopenharmony_ci 488c2ecf20Sopenharmony_ciWhat: /sys/bus/coresight/devices/<memory_map>.stm/traceid 498c2ecf20Sopenharmony_ciDate: April 2016 508c2ecf20Sopenharmony_ciKernelVersion: 4.7 518c2ecf20Sopenharmony_ciContact: Mathieu Poirier <mathieu.poirier@linaro.org> 528c2ecf20Sopenharmony_ciDescription: (RW) Holds the trace ID that will appear in the trace stream 538c2ecf20Sopenharmony_ci coming from this trace entity. 54