1/*
2 * Copyright (c) 2021 Huawei Device Co., Ltd.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 *     http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 */
15
16#ifndef DISP_COMMON_H
17#define DISP_COMMON_H
18#include <stdint.h>
19#include "hdf_log.h"
20
21#ifdef HDF_LOG_TAG
22#undef HDF_LOG_TAG
23#endif
24#define HDF_LOG_TAG HDF_DISP
25
26#define CHECK_NULLPOINTER_RETURN_VALUE(pointer, ret) do { \
27    if ((pointer) == NULL) { \
28        HDF_LOGE("%s: pointer is null", __func__); \
29        return (ret); \
30    } \
31} while (0)
32
33#define CHECK_NULLPOINTER_RETURN(pointer) do { \
34    if ((pointer) == NULL) { \
35        HDF_LOGE("%s: pointer is null", __func__); \
36        return; \
37    } \
38} while (0)
39
40#define DISPLAY_CHK_RETURN(val, ret, ...) \
41    do { \
42        if (val) { \
43            __VA_ARGS__; \
44            return (ret); \
45        } \
46    } while (0)
47
48#define DISPLAY_CHK_RETURN_NOT_VALUE(val, ...) \
49    do { \
50        if (val) { \
51            __VA_ARGS__; \
52            return; \
53        } \
54    } while (0)
55
56enum LayerId {
57    GRA_LAYER_0,
58    GRA_LAYER_1,
59    GRA_LAYER_2,
60    GRA_LAYER_MAX,
61    OV_LAYER_0,
62    OV_LAYER_1,
63    OV_LAYER_2,
64    OV_LAYER_MAX
65};
66
67enum PowerMode {
68    DISP_ON,
69    DISP_OFF,
70};
71
72/* output timing */
73enum IntfSync {
74    OUTPUT_USER = 0,          /* User timing */
75    OUTPUT_PAL,               /* PAL standard */
76    OUTPUT_NTSC,              /* NTSC standard */
77    OUTPUT_1080P24,           /* 1920 x 1080 at 24 Hz. */
78    OUTPUT_1080P25,           /* 1920 x 1080 at 25 Hz. */
79    OUTPUT_1080P30,           /* 1920 x 1080 at 30 Hz. */
80    OUTPUT_720P50,            /* 1280 x  720 at 50 Hz. */
81    OUTPUT_720P60,            /* 1280 x  720 at 60 Hz. */
82    OUTPUT_1080I50,           /* 1920 x 1080 at 50 Hz, interlace. */
83    OUTPUT_1080I60,           /* 1920 x 1080 at 60 Hz, interlace. */
84    OUTPUT_1080P50,           /* 1920 x 1080 at 50 Hz. */
85    OUTPUT_1080P60,           /* 1920 x 1080 at 60 Hz. */
86    OUTPUT_576P50,            /* 720  x  576 at 50 Hz. */
87    OUTPUT_480P60,            /* 720  x  480 at 60 Hz. */
88    OUTPUT_800X600_60,        /* VESA 800 x 600 at 60 Hz (non-interlaced) */
89    OUTPUT_1024X768_60,       /* VESA 1024 x 768 at 60 Hz (non-interlaced) */
90    OUTPUT_1280X1024_60,      /* VESA 1280 x 1024 at 60 Hz (non-interlaced) */
91    OUTPUT_1366X768_60,       /* VESA 1366 x 768 at 60 Hz (non-interlaced) */
92    OUTPUT_1440X900_60,       /* VESA 1440 x 900 at 60 Hz (non-interlaced) CVT Compliant */
93    OUTPUT_1280X800_60,       /* 1280*800@60Hz VGA@60Hz */
94    OUTPUT_1600X1200_60,      /* VESA 1600 x 1200 at 60 Hz (non-interlaced) */
95    OUTPUT_1680X1050_60,      /* VESA 1680 x 1050 at 60 Hz (non-interlaced) */
96    OUTPUT_1920X1200_60,      /* VESA 1920 x 1600 at 60 Hz (non-interlaced) CVT (Reduced Blanking) */
97    OUTPUT_640X480_60,        /* VESA 640 x 480 at 60 Hz (non-interlaced) CVT */
98    OUTPUT_960H_PAL,          /* ITU-R BT.1302 960 x 576 at 50 Hz (interlaced) */
99    OUTPUT_960H_NTSC,         /* ITU-R BT.1302 960 x 480 at 60 Hz (interlaced) */
100    OUTPUT_1920X2160_30,      /* 1920x2160_30 */
101    OUTPUT_2560X1440_30,      /* 2560x1440_30 */
102    OUTPUT_2560X1440_60,      /* 2560x1440_60 */
103    OUTPUT_2560X1600_60,      /* 2560x1600_60 */
104    OUTPUT_3840X2160_24,      /* 3840x2160_24 */
105    OUTPUT_3840X2160_25,      /* 3840x2160_25 */
106    OUTPUT_3840X2160_30,      /* 3840x2160_30 */
107    OUTPUT_3840X2160_50,      /* 3840x2160_50 */
108    OUTPUT_3840X2160_60,      /* 3840x2160_60 */
109    OUTPUT_4096X2160_24,      /* 4096x2160_24 */
110    OUTPUT_4096X2160_25,      /* 4096x2160_25 */
111    OUTPUT_4096X2160_30,      /* 4096x2160_30 */
112    OUTPUT_4096X2160_50,      /* 4096x2160_50 */
113    OUTPUT_4096X2160_60,      /* 4096x2160_60 */
114    OUTPUT_320X240_60,        /* For ota5182 at 60 Hz (8bit) */
115    OUTPUT_320X240_50,        /* For ili9342 at 50 Hz (6bit) */
116    OUTPUT_240X320_50,        /* Hi3559AV100: For ili9341 at 50 Hz (6bit) */
117    OUTPUT_240X320_60,        /* For ili9341 at 60 Hz (16bit) */
118    OUTPUT_800X600_50,        /* For LCD     at 50 Hz (24bit) */
119    OUTPUT_720X1280_60,       /* For MIPI DSI Tx 720 x1280 at 60 Hz */
120    OUTPUT_1080X1920_60,      /* For MIPI DSI Tx 1080x1920 at 60 Hz */
121    OUTPUT_7680X4320_30,      /* For HDMI2.1 at 30 Hz */
122};
123
124struct DispInfo {
125    uint32_t width;
126    uint32_t hbp;
127    uint32_t hfp;
128    uint32_t hsw;
129    uint32_t height;
130    uint32_t vbp;
131    uint32_t vfp;
132    uint32_t vsw;
133    uint32_t frameRate;
134    uint32_t intfType;
135    enum IntfSync intfSync;
136    uint32_t minLevel;
137    uint32_t maxLevel;
138    uint32_t defLevel;
139};
140#endif // DISP_COMMON_H
141