1e41f4b71Sopenharmony_ci# GPIO 2e41f4b71Sopenharmony_ci 3e41f4b71Sopenharmony_ci## Overview 4e41f4b71Sopenharmony_ci 5e41f4b71Sopenharmony_ci### Function 6e41f4b71Sopenharmony_ci 7e41f4b71Sopenharmony_ciA general-purpose input/output (GPIO) controller manages all GPIO pins by group. Each group of GPIO pins is associated with one or more registers. The GPIO controller manages the pins by reading data from and writing data to the registers. 8e41f4b71Sopenharmony_ci 9e41f4b71Sopenharmony_ciThe GPIO module provides APIs for performing operations on GPIO pins, including: 10e41f4b71Sopenharmony_ci 11e41f4b71Sopenharmony_ci- Setting the pin direction, which can be input or output (high impedance is not supported currently) 12e41f4b71Sopenharmony_ci- Reading and writing the pin level, which can be low or high 13e41f4b71Sopenharmony_ci- Setting an interrupt service routine (ISR) function and interrupt trigger mode for a pin 14e41f4b71Sopenharmony_ci- Enabling or disabling interrupts for a pin 15e41f4b71Sopenharmony_ci 16e41f4b71Sopenharmony_ci### Basic Concepts 17e41f4b71Sopenharmony_ci 18e41f4b71Sopenharmony_ciA GPIO can be used as an input, an output, or both, and is controllable by software. 19e41f4b71Sopenharmony_ci 20e41f4b71Sopenharmony_ci- GPIO input 21e41f4b71Sopenharmony_ci 22e41f4b71Sopenharmony_ci When a GPIO is used as an input, it reads the level state (high or low) of each pin. Common input modes include analog input, floating input, pull-up input, and pull-down input. 23e41f4b71Sopenharmony_ci 24e41f4b71Sopenharmony_ci- GPIO output 25e41f4b71Sopenharmony_ci 26e41f4b71Sopenharmony_ci When a GPIO is used as an output, it sets the pin level. Common output modes include open-drain output, push-pull output, multiplexed open-drain output, and multiplexed push-pull output. 27e41f4b71Sopenharmony_ci 28e41f4b71Sopenharmony_ci### Working Principles 29e41f4b71Sopenharmony_ci 30e41f4b71Sopenharmony_ciIn the Hardware Driver Foundation (HDF), the GPIO module uses the unified service mode for API adaptation. In this mode, a device service is used as the GPIO manager to handle access requests from the devices of the same type in a unified manner. The unified service mode applies to the scenario where there are many device objects of the same type. If the independent service mode is used in this case, more device nodes need to be configured and more memory resources will be consumed. The following figure shows the unified service mode. 31e41f4b71Sopenharmony_ci 32e41f4b71Sopenharmony_ciIn the unified service mode, the core layer manages all controllers in a unified manner and publishes a service for the interface layer. That is, the driver does not need to publish a service for each controller. 33e41f4b71Sopenharmony_ci 34e41f4b71Sopenharmony_ciThe GPIO module is divided into the following layers: 35e41f4b71Sopenharmony_ci 36e41f4b71Sopenharmony_ci- Interface layer: provides APIs for operating GPIO pins. 37e41f4b71Sopenharmony_ci- Core layer: provides the capabilities of adding and removing the GPIO controller and managing GPIO pins. This layer interacts with the adaptation layer through hook functions to allow the GPIO chip drivers of different vendors to quickly access the HDF. 38e41f4b71Sopenharmony_ci- Adaptation layer: instantiates hook functions to implement specific features. 39e41f4b71Sopenharmony_ci 40e41f4b71Sopenharmony_ci**Figure 1** Unified service mode 41e41f4b71Sopenharmony_ci 42e41f4b71Sopenharmony_ci 43e41f4b71Sopenharmony_ci 44e41f4b71Sopenharmony_ci## Usage Guidelines 45e41f4b71Sopenharmony_ci 46e41f4b71Sopenharmony_ci### When to Use 47e41f4b71Sopenharmony_ci 48e41f4b71Sopenharmony_ciAs a concept at the software layer, GPIO is used to manage GPIO pin resources. You can use the GPIO APIs to control pins. 49e41f4b71Sopenharmony_ci 50e41f4b71Sopenharmony_ci### Available APIs 51e41f4b71Sopenharmony_ci 52e41f4b71Sopenharmony_ciThe following table describes the APIs provided by the GPIO module. 53e41f4b71Sopenharmony_ci 54e41f4b71Sopenharmony_ci**Table 1** GPIO driver APIs 55e41f4b71Sopenharmony_ci 56e41f4b71Sopenharmony_ci| API | Description | 57e41f4b71Sopenharmony_ci| ------------------------------------------------------------ | ------------------------------ | 58e41f4b71Sopenharmony_ci| GpioGetByName(const char *gpioName) | Obtains the GPIO pin number. | 59e41f4b71Sopenharmony_ci| int32_t GpioRead(uint16_t gpio, uint16_t *val) | Reads the level of a GPIO pin. | 60e41f4b71Sopenharmony_ci| int32_t GpioWrite(uint16_t gpio, uint16_t val) | Writes the level of a GPIO pin. | 61e41f4b71Sopenharmony_ci| int32_t GpioGetDir(uint16_t gpio, uint16_t *dir) | Obtains the direction of a GPIO pin. | 62e41f4b71Sopenharmony_ci| int32_t GpioSetDir(uint16_t gpio, uint16_t dir) | Sets the direction for a GPIO pin. | 63e41f4b71Sopenharmony_ci| int32_t GpioUnsetIrq(uint16_t gpio, void *arg); | Cancels the ISR function for a GPIO pin. | 64e41f4b71Sopenharmony_ci| int32_t GpioSetIrq(uint16_t gpio, uint16_t mode, GpioIrqFunc func, void *arg) | Sets an ISR function for a GPIO pin. | 65e41f4b71Sopenharmony_ci| int32_t GpioEnableIrq(uint16_t gpio) | Enables interrupts for a GPIO pin. | 66e41f4b71Sopenharmony_ci| int32_t GpioDisableIrq(uint16_t gpio) | Disables interrupts for a GPIO pin. | 67e41f4b71Sopenharmony_ci 68e41f4b71Sopenharmony_ci> **NOTE** 69e41f4b71Sopenharmony_ci> 70e41f4b71Sopenharmony_ci>All GPIO APIs described in this document can be used in kernel mode and user mode. 71e41f4b71Sopenharmony_ci 72e41f4b71Sopenharmony_ci### How to Develop 73e41f4b71Sopenharmony_ci 74e41f4b71Sopenharmony_ciThe fillowing figure shows how to use the GPIO APIs to manage pins. In the APIs, a GPIO pin is identified by the pin number. 75e41f4b71Sopenharmony_ci 76e41f4b71Sopenharmony_ci**Figure 2** Using GPIO driver APIs 77e41f4b71Sopenharmony_ci 78e41f4b71Sopenharmony_ci 79e41f4b71Sopenharmony_ci 80e41f4b71Sopenharmony_ci#### Determining the GPIO Pin Number 81e41f4b71Sopenharmony_ci 82e41f4b71Sopenharmony_ciYou can determine the GPIO pin number in either of the following ways: 83e41f4b71Sopenharmony_ci 84e41f4b71Sopenharmony_ci- Calculating the pin number based on the system on chip (SoC) 85e41f4b71Sopenharmony_ci 86e41f4b71Sopenharmony_ci The method for determining the GPIO pin number varies depending on the GPIO controller model, parameters, and controller driver of the SoC. 87e41f4b71Sopenharmony_ci 88e41f4b71Sopenharmony_ci - Hi3516D V300 89e41f4b71Sopenharmony_ci 90e41f4b71Sopenharmony_ci A controller manages 12 groups of GPIO pins. Each group contains 8 GPIO pins. The group number ranges from 0 to 11. 91e41f4b71Sopenharmony_ci 92e41f4b71Sopenharmony_ci GPIO pin number = GPIO group number x Number of GPIO pins in each group + Offset in the group 93e41f4b71Sopenharmony_ci 94e41f4b71Sopenharmony_ci Example: 95e41f4b71Sopenharmony_ci 96e41f4b71Sopenharmony_ci GPIO pin number of GPIO10_3 = 10 x 8 + 3 = 83 97e41f4b71Sopenharmony_ci 98e41f4b71Sopenharmony_ci - Hi3518E V300 99e41f4b71Sopenharmony_ci 100e41f4b71Sopenharmony_ci A controller manages 10 groups of GPIO pins. Each group contains 10 GPIO pins. The group number ranges from 0 to 9. 101e41f4b71Sopenharmony_ci 102e41f4b71Sopenharmony_ci GPIO pin number = GPIO group number x Number of GPIO pins in each group + Offset in the group 103e41f4b71Sopenharmony_ci 104e41f4b71Sopenharmony_ci Example: 105e41f4b71Sopenharmony_ci 106e41f4b71Sopenharmony_ci GPIO pin number of GPIO7_3 = 7 x 10 + 3 = 73 107e41f4b71Sopenharmony_ci 108e41f4b71Sopenharmony_ci- Obtaining the pin number based on the pin alias 109e41f4b71Sopenharmony_ci 110e41f4b71Sopenharmony_ci Use **GpioGetByName()** to obtain the pin number based on the pin alias. The global pin number is returned. 111e41f4b71Sopenharmony_ci 112e41f4b71Sopenharmony_ci ```c 113e41f4b71Sopenharmony_ci GpioGetByName(const char *gpioName); 114e41f4b71Sopenharmony_ci ``` 115e41f4b71Sopenharmony_ci 116e41f4b71Sopenharmony_ci#### Setting the GPIO Pin Direction 117e41f4b71Sopenharmony_ci 118e41f4b71Sopenharmony_ciBefore performing read/write operations on a GPIO pin, use **GpioSetDir()** to set the pin direction. 119e41f4b71Sopenharmony_ci 120e41f4b71Sopenharmony_ci```c 121e41f4b71Sopenharmony_ciint32_t GpioSetDir(uint16_t gpio, uint16_t dir); 122e41f4b71Sopenharmony_ci``` 123e41f4b71Sopenharmony_ci 124e41f4b71Sopenharmony_ci**Table 2** Description of GpioSetDir 125e41f4b71Sopenharmony_ci 126e41f4b71Sopenharmony_ci| **Parameter** | **Description** | 127e41f4b71Sopenharmony_ci| ---------- | ------------------ | 128e41f4b71Sopenharmony_ci| gpio | GPIO pin number.| 129e41f4b71Sopenharmony_ci| dir | Direction to set. | 130e41f4b71Sopenharmony_ci| **Return Value**| **Description** | 131e41f4b71Sopenharmony_ci| 0 | The operation is successful. | 132e41f4b71Sopenharmony_ci| Negative value | The operation failed. | 133e41f4b71Sopenharmony_ci 134e41f4b71Sopenharmony_ciExample: Set the direction of GPIO pin 3 to output. 135e41f4b71Sopenharmony_ci 136e41f4b71Sopenharmony_ci```c 137e41f4b71Sopenharmony_ciint32_t ret; 138e41f4b71Sopenharmony_ci 139e41f4b71Sopenharmony_ciret = GpioSetDir(3, GPIO_DIR_OUT); // Set GPIO pin 3 as an output. 140e41f4b71Sopenharmony_ciif (ret != 0) { 141e41f4b71Sopenharmony_ci HDF_LOGE("GpioSetDir: failed, ret %d\n", ret); 142e41f4b71Sopenharmony_ci return ret; 143e41f4b71Sopenharmony_ci} 144e41f4b71Sopenharmony_ci``` 145e41f4b71Sopenharmony_ci 146e41f4b71Sopenharmony_ci#### Obtaining the GPIO Pin Direction 147e41f4b71Sopenharmony_ci 148e41f4b71Sopenharmony_ciUse **GpioGetDir()** to obtain the GPIO pin direction. 149e41f4b71Sopenharmony_ci 150e41f4b71Sopenharmony_ci```c 151e41f4b71Sopenharmony_ciint32_t GpioGetDir(uint16_t gpio, uint16_t *dir); 152e41f4b71Sopenharmony_ci``` 153e41f4b71Sopenharmony_ci 154e41f4b71Sopenharmony_ci**Table 3** Description of GpioGetDir 155e41f4b71Sopenharmony_ci 156e41f4b71Sopenharmony_ci| **Parameter** | **Description** | 157e41f4b71Sopenharmony_ci| ---------- | ------------------ | 158e41f4b71Sopenharmony_ci| gpio | GPIO pin number.| 159e41f4b71Sopenharmony_ci| dir | Pointer to the direction value obtained. | 160e41f4b71Sopenharmony_ci| **Return Value**| **Description** | 161e41f4b71Sopenharmony_ci| 0 | The operation is successful. | 162e41f4b71Sopenharmony_ci| Negative value | The operation failed. | 163e41f4b71Sopenharmony_ci 164e41f4b71Sopenharmony_ciExample: Obtain the direction of GPIO pin 3. 165e41f4b71Sopenharmony_ci 166e41f4b71Sopenharmony_ci```c 167e41f4b71Sopenharmony_ciint32_t ret; 168e41f4b71Sopenharmony_ciuin16_t dir; 169e41f4b71Sopenharmony_ci 170e41f4b71Sopenharmony_ciret = GpioGetDir(3, &dir); // Obtain the direction of GPIO pin 3. 171e41f4b71Sopenharmony_ciif (ret != 0) { 172e41f4b71Sopenharmony_ci HDF_LOGE("GpioGetDir: failed, ret %d\n", ret); 173e41f4b71Sopenharmony_ci return ret; 174e41f4b71Sopenharmony_ci} 175e41f4b71Sopenharmony_ci``` 176e41f4b71Sopenharmony_ci 177e41f4b71Sopenharmony_ci#### Reading the GPIO Pin Level 178e41f4b71Sopenharmony_ci 179e41f4b71Sopenharmony_ciUse **GpioRead()** to read the level of a GPIO pin. 180e41f4b71Sopenharmony_ci 181e41f4b71Sopenharmony_ci```c 182e41f4b71Sopenharmony_ciint32_t GpioRead(uint16_t gpio, uint16_t *val); 183e41f4b71Sopenharmony_ci``` 184e41f4b71Sopenharmony_ci 185e41f4b71Sopenharmony_ci**Table 4** Description of GpioRead 186e41f4b71Sopenharmony_ci 187e41f4b71Sopenharmony_ci| **Parameter** | **Description** | 188e41f4b71Sopenharmony_ci| ---------- | -------------------- | 189e41f4b71Sopenharmony_ci| gpio | GPIO pin number. | 190e41f4b71Sopenharmony_ci| val | Pointer to the level value read. | 191e41f4b71Sopenharmony_ci| **Return Value**| **Description** | 192e41f4b71Sopenharmony_ci| 0 | The operation is successful. | 193e41f4b71Sopenharmony_ci| Negative value | The operation failed. | 194e41f4b71Sopenharmony_ci 195e41f4b71Sopenharmony_ciExample: Read the level of GPIO pin 3. 196e41f4b71Sopenharmony_ci 197e41f4b71Sopenharmony_ci```c 198e41f4b71Sopenharmony_ciint32_t ret; 199e41f4b71Sopenharmony_ciuint16_t val; 200e41f4b71Sopenharmony_ci 201e41f4b71Sopenharmony_ciret = GpioRead(3, &val); // Read the level of GPIO pin 3. 202e41f4b71Sopenharmony_ciif (ret != 0) { 203e41f4b71Sopenharmony_ci HDF_LOGE("GpioRead: failed, ret %d\n", ret); 204e41f4b71Sopenharmony_ci return ret; 205e41f4b71Sopenharmony_ci} 206e41f4b71Sopenharmony_ci``` 207e41f4b71Sopenharmony_ci 208e41f4b71Sopenharmony_ci#### Writing the GPIO Pin Level 209e41f4b71Sopenharmony_ci 210e41f4b71Sopenharmony_ciUse **GpioWrite()** to write the level for a GPIO pin. 211e41f4b71Sopenharmony_ci 212e41f4b71Sopenharmony_ci```c 213e41f4b71Sopenharmony_ciint32_t GpioWrite(uint16_t gpio, uint16_t val); 214e41f4b71Sopenharmony_ci``` 215e41f4b71Sopenharmony_ci 216e41f4b71Sopenharmony_ci**Table 5** Description of GpioWrite 217e41f4b71Sopenharmony_ci 218e41f4b71Sopenharmony_ci| **Parameter** | **Description** | 219e41f4b71Sopenharmony_ci| ---------- | ------------------ | 220e41f4b71Sopenharmony_ci| gpio | GPIO pin number.| 221e41f4b71Sopenharmony_ci| val | Level to write. | 222e41f4b71Sopenharmony_ci| **Return Value**| **Description** | 223e41f4b71Sopenharmony_ci| 0 | The operation is successful. | 224e41f4b71Sopenharmony_ci| Negative value | The operation failed. | 225e41f4b71Sopenharmony_ci 226e41f4b71Sopenharmony_ciExample: Write a low level value to the register of GPIO pin 3. 227e41f4b71Sopenharmony_ci 228e41f4b71Sopenharmony_ci```c 229e41f4b71Sopenharmony_ciint32_t ret; 230e41f4b71Sopenharmony_ci 231e41f4b71Sopenharmony_ciret = GpioWrite(3, GPIO_VAL_LOW); // Write a low level value to the register of GPIO pin 3. 232e41f4b71Sopenharmony_ciif (ret != 0) { 233e41f4b71Sopenharmony_ci HDF_LOGE("GpioRead: failed, ret %d\n", ret); 234e41f4b71Sopenharmony_ci return ret; 235e41f4b71Sopenharmony_ci} 236e41f4b71Sopenharmony_ci``` 237e41f4b71Sopenharmony_ci 238e41f4b71Sopenharmony_ci#### Setting an ISR Function for a GPIO Pin 239e41f4b71Sopenharmony_ci 240e41f4b71Sopenharmony_ciUse **GpioSetIrq()** to set an ISR function for a GPIO pin. 241e41f4b71Sopenharmony_ci 242e41f4b71Sopenharmony_ci```c 243e41f4b71Sopenharmony_ciint32_t GpioSetIrq(uint16_t gpio, uint16_t mode, GpioIrqFunc func, void *arg); 244e41f4b71Sopenharmony_ci``` 245e41f4b71Sopenharmony_ci 246e41f4b71Sopenharmony_ci**Table 6** Description of GpioSetIrq 247e41f4b71Sopenharmony_ci 248e41f4b71Sopenharmony_ci| **Parameter** | **Description** | 249e41f4b71Sopenharmony_ci| ---------- | ------------------------ | 250e41f4b71Sopenharmony_ci| gpio | GPIO pin number. | 251e41f4b71Sopenharmony_ci| mode | Interrupt trigger mode. | 252e41f4b71Sopenharmony_ci| func | ISR function to set. | 253e41f4b71Sopenharmony_ci| arg | Pointer to the parameters passed to the ISR function.| 254e41f4b71Sopenharmony_ci| **Return Value**| **Description** | 255e41f4b71Sopenharmony_ci| 0 | The operation is successful. | 256e41f4b71Sopenharmony_ci| Negative value | The operation failed. | 257e41f4b71Sopenharmony_ci 258e41f4b71Sopenharmony_ci>  **CAUTION**<br/> 259e41f4b71Sopenharmony_ci> Only one ISR function can be set for a GPIO pin. If **GpioSetIrq** is called repeatedly, the previous IRS function will be replaced. 260e41f4b71Sopenharmony_ci 261e41f4b71Sopenharmony_ci#### Canceling the ISR Function for a GPIO Pin 262e41f4b71Sopenharmony_ci 263e41f4b71Sopenharmony_ciIf the ISR function is no longer required, call **GpioUnsetIrq()** to cancel it. 264e41f4b71Sopenharmony_ci 265e41f4b71Sopenharmony_ci```c 266e41f4b71Sopenharmony_ciint32_t GpioUnsetIrq(uint16_t gpio, void *arg); 267e41f4b71Sopenharmony_ci``` 268e41f4b71Sopenharmony_ci 269e41f4b71Sopenharmony_ci**Table 7** Description of GpioUnsetIrq 270e41f4b71Sopenharmony_ci 271e41f4b71Sopenharmony_ci| **Parameter** | **Description** | 272e41f4b71Sopenharmony_ci| ---------- | -------------- | 273e41f4b71Sopenharmony_ci| gpio | GPIO pin number. | 274e41f4b71Sopenharmony_ci| arg | Pointer to the GPIO interrupt parameters. | 275e41f4b71Sopenharmony_ci| **Return Value**| **Description**| 276e41f4b71Sopenharmony_ci| 0 | The operation is successful. | 277e41f4b71Sopenharmony_ci| Negative value | The operation failed. | 278e41f4b71Sopenharmony_ci 279e41f4b71Sopenharmony_ci#### Enabling Interrupts for a GPIO Pin 280e41f4b71Sopenharmony_ci 281e41f4b71Sopenharmony_ciAfter the ISR function is set, call **GpioEnableIrq()** to enable interrupts for the GPIO pin. 282e41f4b71Sopenharmony_ci 283e41f4b71Sopenharmony_ci```c 284e41f4b71Sopenharmony_ciint32_t GpioEnableIrq(uint16_t gpio); 285e41f4b71Sopenharmony_ci``` 286e41f4b71Sopenharmony_ci 287e41f4b71Sopenharmony_ci**Table 8** Description of GpioEnableIrq 288e41f4b71Sopenharmony_ci 289e41f4b71Sopenharmony_ci| **Parameter** | **Description** | 290e41f4b71Sopenharmony_ci| ---------- | -------------- | 291e41f4b71Sopenharmony_ci| gpio | GPIO pin number. | 292e41f4b71Sopenharmony_ci| **Return Value**| **Description**| 293e41f4b71Sopenharmony_ci| 0 | The operation is successful. | 294e41f4b71Sopenharmony_ci| Negative value | The operation failed. | 295e41f4b71Sopenharmony_ci 296e41f4b71Sopenharmony_ci>  **CAUTION**<br/> 297e41f4b71Sopenharmony_ci> The configured ISR function can be responded only after interrupts are enabled for the GPIO pin. 298e41f4b71Sopenharmony_ci 299e41f4b71Sopenharmony_ci#### Disabling Interrupts for a GPIO Pin 300e41f4b71Sopenharmony_ci 301e41f4b71Sopenharmony_ciUse **GpioDisableIrq()** to disable interrupts for a pin. 302e41f4b71Sopenharmony_ci 303e41f4b71Sopenharmony_ci```c 304e41f4b71Sopenharmony_ciint32_t GpioDisableIrq(uint16_t gpio); 305e41f4b71Sopenharmony_ci``` 306e41f4b71Sopenharmony_ci**Table 9** Description of GpioDisableIrq 307e41f4b71Sopenharmony_ci 308e41f4b71Sopenharmony_ci| **Parameter** | **Description** | 309e41f4b71Sopenharmony_ci| ---------- | -------------- | 310e41f4b71Sopenharmony_ci| gpio | GPIO pin number. | 311e41f4b71Sopenharmony_ci| **Return Value**| **Description**| 312e41f4b71Sopenharmony_ci| 0 | The operation is successful. | 313e41f4b71Sopenharmony_ci| Negative value | The operation failed. | 314e41f4b71Sopenharmony_ci 315e41f4b71Sopenharmony_ciExample: 316e41f4b71Sopenharmony_ci 317e41f4b71Sopenharmony_ci```c 318e41f4b71Sopenharmony_ci/* Set an ISR function. */ 319e41f4b71Sopenharmony_ciint32_t MyCallBackFunc(uint16_t gpio, void *data) 320e41f4b71Sopenharmony_ci{ 321e41f4b71Sopenharmony_ci HDF_LOGI("%s: gpio:%u interrupt service in data\n", __func__, gpio); 322e41f4b71Sopenharmony_ci return 0; 323e41f4b71Sopenharmony_ci} 324e41f4b71Sopenharmony_ci 325e41f4b71Sopenharmony_ciint32_t ret; 326e41f4b71Sopenharmony_ci/* Set the ISR function to MyCallBackFunc, with input parameter of NULL and the interrupt trigger mode of rising edge. */ 327e41f4b71Sopenharmony_ciret = GpioSetIrq(3, OSAL_IRQF_TRIGGER_RISING, MyCallBackFunc, NULL); 328e41f4b71Sopenharmony_ciif (ret != 0) { 329e41f4b71Sopenharmony_ci HDF_LOGE("GpioSetIrq: failed, ret %d\n", ret); 330e41f4b71Sopenharmony_ci return ret; 331e41f4b71Sopenharmony_ci} 332e41f4b71Sopenharmony_ci 333e41f4b71Sopenharmony_ci/* Enable interrupts for GPIO pin 3. */ 334e41f4b71Sopenharmony_ciret = GpioEnableIrq(3); 335e41f4b71Sopenharmony_ciif (ret != 0) { 336e41f4b71Sopenharmony_ci HDF_LOGE("GpioEnableIrq: failed, ret %d\n", ret); 337e41f4b71Sopenharmony_ci return ret; 338e41f4b71Sopenharmony_ci} 339e41f4b71Sopenharmony_ci 340e41f4b71Sopenharmony_ci/* Disable interrupts for GPIO pin 3. */ 341e41f4b71Sopenharmony_ciret = GpioDisableIrq(3); 342e41f4b71Sopenharmony_ciif (ret != 0) { 343e41f4b71Sopenharmony_ci HDF_LOGE("GpioDisableIrq: failed, ret %d\n", ret); 344e41f4b71Sopenharmony_ci return ret; 345e41f4b71Sopenharmony_ci} 346e41f4b71Sopenharmony_ci 347e41f4b71Sopenharmony_ci/* Cancel the ISR function for GPIO pin 3. */ 348e41f4b71Sopenharmony_ciret = GpioUnsetIrq(3, NULL); 349e41f4b71Sopenharmony_ciif (ret != 0) { 350e41f4b71Sopenharmony_ci HDF_LOGE("GpioUnSetIrq: failed, ret %d\n", ret); 351e41f4b71Sopenharmony_ci return ret; 352e41f4b71Sopenharmony_ci} 353e41f4b71Sopenharmony_ci``` 354e41f4b71Sopenharmony_ci 355e41f4b71Sopenharmony_ci## Example 356e41f4b71Sopenharmony_ci 357e41f4b71Sopenharmony_ciThe following example shows how to trigger an interrupt for a GPIO pin. The procedure is as follows: 358e41f4b71Sopenharmony_ci 359e41f4b71Sopenharmony_ci1. Select an idle GPIO pin, for example, pin GPIO10_3 on a Hi3516D V300 development board. The pin number of GPIO10_3 is 83. You can select an idle GPIO pin as required. 360e41f4b71Sopenharmony_ci2. Set an ISR function for the pin, with the interrupt trigger mode of rising edge and falling edge. 361e41f4b71Sopenharmony_ci3. Write high and low levels to the pin alternately, and observe the execution of the ISR function. 362e41f4b71Sopenharmony_ci 363e41f4b71Sopenharmony_ciSample code: 364e41f4b71Sopenharmony_ci 365e41f4b71Sopenharmony_ci```c 366e41f4b71Sopenharmony_ci#include "gpio_if.h" 367e41f4b71Sopenharmony_ci#include "hdf_log.h" 368e41f4b71Sopenharmony_ci#include "osal_irq.h" 369e41f4b71Sopenharmony_ci#include "osal_time.h" 370e41f4b71Sopenharmony_ci 371e41f4b71Sopenharmony_cistatic uint32_t g_irqCnt; 372e41f4b71Sopenharmony_ci 373e41f4b71Sopenharmony_ci/* ISR function */ 374e41f4b71Sopenharmony_cistatic int32_t TestCaseGpioIrqHandler(uint16_t gpio, void *data) 375e41f4b71Sopenharmony_ci{ 376e41f4b71Sopenharmony_ci HDF_LOGE("%s: irq triggered! on gpio:%u, in data", __func__, gpio); 377e41f4b71Sopenharmony_ci g_irqCnt++; /* If the ISR function is triggered, the global interrupt counter is incremented by 1. */ 378e41f4b71Sopenharmony_ci return GpioDisableIrq(gpio); 379e41f4b71Sopenharmony_ci} 380e41f4b71Sopenharmony_ci 381e41f4b71Sopenharmony_ci/* Test case function */ 382e41f4b71Sopenharmony_cistatic int32_t TestCaseGpioIrqEdge(void) 383e41f4b71Sopenharmony_ci{ 384e41f4b71Sopenharmony_ci int32_t ret; 385e41f4b71Sopenharmony_ci uint16_t valRead; 386e41f4b71Sopenharmony_ci uint16_t mode; 387e41f4b71Sopenharmony_ci uint16_t gpio = 83; /* Number of the GPIO pin to test */ 388e41f4b71Sopenharmony_ci uint32_t timeout; 389e41f4b71Sopenharmony_ci 390e41f4b71Sopenharmony_ci /* Set the pin direction to output. */ 391e41f4b71Sopenharmony_ci ret = GpioSetDir(gpio, GPIO_DIR_OUT); 392e41f4b71Sopenharmony_ci if (ret != HDF_SUCCESS) { 393e41f4b71Sopenharmony_ci HDF_LOGE("%s: set dir fail! ret:%d\n", __func__, ret); 394e41f4b71Sopenharmony_ci return ret; 395e41f4b71Sopenharmony_ci } 396e41f4b71Sopenharmony_ci 397e41f4b71Sopenharmony_ci /* Disable interrupts of the pin. */ 398e41f4b71Sopenharmony_ci ret = GpioDisableIrq(gpio); 399e41f4b71Sopenharmony_ci if (ret != HDF_SUCCESS) { 400e41f4b71Sopenharmony_ci HDF_LOGE("%s: disable irq fail! ret:%d\n", __func__, ret); 401e41f4b71Sopenharmony_ci return ret; 402e41f4b71Sopenharmony_ci } 403e41f4b71Sopenharmony_ci 404e41f4b71Sopenharmony_ci /* Set the ISR function for the pin. The trigger mode is both rising edge and falling edge. */ 405e41f4b71Sopenharmony_ci mode = OSAL_IRQF_TRIGGER_RISING | OSAL_IRQF_TRIGGER_FALLING; 406e41f4b71Sopenharmony_ci HDF_LOGE("%s: mode:%0x\n", __func__, mode); 407e41f4b71Sopenharmony_ci ret = GpioSetIrq(gpio, mode, TestCaseGpioIrqHandler, NULL); 408e41f4b71Sopenharmony_ci if (ret != HDF_SUCCESS) { 409e41f4b71Sopenharmony_ci HDF_LOGE("%s: set irq fail! ret:%d\n", __func__, ret); 410e41f4b71Sopenharmony_ci return ret; 411e41f4b71Sopenharmony_ci } 412e41f4b71Sopenharmony_ci 413e41f4b71Sopenharmony_ci /* Enable interrupts for the pin. */ 414e41f4b71Sopenharmony_ci ret = GpioEnableIrq(gpio); 415e41f4b71Sopenharmony_ci if (ret != HDF_SUCCESS) { 416e41f4b71Sopenharmony_ci HDF_LOGE("%s: enable irq fail! ret:%d\n", __func__, ret); 417e41f4b71Sopenharmony_ci (void)GpioUnsetIrq(gpio, NULL); 418e41f4b71Sopenharmony_ci return ret; 419e41f4b71Sopenharmony_ci } 420e41f4b71Sopenharmony_ci 421e41f4b71Sopenharmony_ci g_irqCnt = 0; /* Reset the global interrupt counter. */ 422e41f4b71Sopenharmony_ci timeout = 0; /* Clear the waiting time. */ 423e41f4b71Sopenharmony_ci /* Wait for the ISR function to trigger for this pin. The timeout duration is 1000 ms. */ 424e41f4b71Sopenharmony_ci while (g_irqCnt <= 0 && timeout < 1000) { 425e41f4b71Sopenharmony_ci (void)GpioRead(gpio, &valRead); 426e41f4b71Sopenharmony_ci (void)GpioWrite(gpio, (valRead == GPIO_VAL_LOW) ? GPIO_VAL_HIGH : GPIO_VAL_LOW); 427e41f4b71Sopenharmony_ci HDF_LOGE("%s: wait irq timeout:%u\n", __func__, timeout); 428e41f4b71Sopenharmony_ci OsalMDelay(200); /* wait for irq trigger */ 429e41f4b71Sopenharmony_ci timeout += 200; 430e41f4b71Sopenharmony_ci } 431e41f4b71Sopenharmony_ci (void)GpioUnsetIrq(gpio, NULL); 432e41f4b71Sopenharmony_ci return (g_irqCnt > 0) ? HDF_SUCCESS : HDF_FAILURE; 433e41f4b71Sopenharmony_ci} 434e41f4b71Sopenharmony_ci``` 435