13d0407baSopenharmony_ci/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 23d0407baSopenharmony_ci/* 33d0407baSopenharmony_ci * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 43d0407baSopenharmony_ci */ 53d0407baSopenharmony_ci 63d0407baSopenharmony_ci#ifndef _DT_BINDINGS_PHY_SNPS_PCIE3 73d0407baSopenharmony_ci#define _DT_BINDINGS_PHY_SNPS_PCIE3 83d0407baSopenharmony_ci 93d0407baSopenharmony_ci/* 103d0407baSopenharmony_ci * pcie30_phy_mode[2:0] 113d0407baSopenharmony_ci * bit2: aggregation 123d0407baSopenharmony_ci * bit1: bifurcation for port 1 133d0407baSopenharmony_ci * bit0: bifurcation for port 0 143d0407baSopenharmony_ci */ 153d0407baSopenharmony_ci#define PHY_MODE_PCIE_AGGREGATION 4 /* PCIe3x4 */ 163d0407baSopenharmony_ci#define PHY_MODE_PCIE_NANBNB 0 /* P1:PCIe3x2 + P0:PCIe3x2 */ 173d0407baSopenharmony_ci#define PHY_MODE_PCIE_NANBBI 1 /* P1:PCIe3x2 + P0:PCIe3x1*2 */ 183d0407baSopenharmony_ci#define PHY_MODE_PCIE_NABINB 2 /* P1:PCIe3x1*2 + P0:PCIe3x2 */ 193d0407baSopenharmony_ci#define PHY_MODE_PCIE_NABIBI 3 /* P1:PCIe3x1*2 + P0:PCIe3x1*2 */ 203d0407baSopenharmony_ci 213d0407baSopenharmony_ci#endif /* _DT_BINDINGS_PHY_SNPS_PCIE3 */ 22