13d0407baSopenharmony_ci/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 23d0407baSopenharmony_ci/* 33d0407baSopenharmony_ci * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 43d0407baSopenharmony_ci * Author: Sandy Huang <hjc@rock-chips.com> 53d0407baSopenharmony_ci */ 63d0407baSopenharmony_ci 73d0407baSopenharmony_ci#ifndef ROCKCHIP_DRM_LOGO_H 83d0407baSopenharmony_ci#define ROCKCHIP_DRM_LOGO_H 93d0407baSopenharmony_ci 103d0407baSopenharmony_cistruct rockchip_drm_mode_set { 113d0407baSopenharmony_ci struct list_head head; 123d0407baSopenharmony_ci struct drm_framebuffer *fb; 133d0407baSopenharmony_ci struct rockchip_drm_sub_dev *sub_dev; 143d0407baSopenharmony_ci struct drm_crtc *crtc; 153d0407baSopenharmony_ci struct drm_display_mode *mode; 163d0407baSopenharmony_ci int clock; 173d0407baSopenharmony_ci int hdisplay; 183d0407baSopenharmony_ci int vdisplay; 193d0407baSopenharmony_ci int vrefresh; 203d0407baSopenharmony_ci int flags; 213d0407baSopenharmony_ci int picture_aspect_ratio; 223d0407baSopenharmony_ci int crtc_hsync_end; 233d0407baSopenharmony_ci int crtc_vsync_end; 243d0407baSopenharmony_ci 253d0407baSopenharmony_ci int left_margin; 263d0407baSopenharmony_ci int right_margin; 273d0407baSopenharmony_ci int top_margin; 283d0407baSopenharmony_ci int bottom_margin; 293d0407baSopenharmony_ci 303d0407baSopenharmony_ci unsigned int brightness; 313d0407baSopenharmony_ci unsigned int contrast; 323d0407baSopenharmony_ci unsigned int saturation; 333d0407baSopenharmony_ci unsigned int hue; 343d0407baSopenharmony_ci 353d0407baSopenharmony_ci bool mode_changed; 363d0407baSopenharmony_ci int ratio; 373d0407baSopenharmony_ci}; 383d0407baSopenharmony_ci 393d0407baSopenharmony_civoid rockchip_drm_show_logo(struct drm_device *drm_dev); 403d0407baSopenharmony_civoid rockchip_free_loader_memory(struct drm_device *drm); 413d0407baSopenharmony_ci 423d0407baSopenharmony_ci#endif 43